1 /* 2 * Copyright (C) 2010 Heiko Schocher <hs@denx.de> 3 * 4 * based on: 5 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __IMX27LITE_COMMON_CONFIG_H 11 #define __IMX27LITE_COMMON_CONFIG_H 12 13 /* 14 * SoC Configuration 15 */ 16 #define CONFIG_MX27 17 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ 18 19 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 20 #define CONFIG_SETUP_MEMORY_TAGS 1 21 #define CONFIG_INITRD_TAG 1 22 23 /* 24 * Lowlevel configuration 25 */ 26 #define SDRAM_ESDCFG_REGISTER_VAL(cas) \ 27 (ESDCFG_TRC(10) | \ 28 ESDCFG_TRCD(3) | \ 29 ESDCFG_TCAS(cas) | \ 30 ESDCFG_TRRD(1) | \ 31 ESDCFG_TRAS(5) | \ 32 ESDCFG_TWR | \ 33 ESDCFG_TMRD(2) | \ 34 ESDCFG_TRP(2) | \ 35 ESDCFG_TXP(3)) 36 37 #define SDRAM_ESDCTL_REGISTER_VAL \ 38 (ESDCTL_PRCT(0) | \ 39 ESDCTL_BL | \ 40 ESDCTL_PWDT(0) | \ 41 ESDCTL_SREFR(3) | \ 42 ESDCTL_DSIZ_32 | \ 43 ESDCTL_COL10 | \ 44 ESDCTL_ROW13 | \ 45 ESDCTL_SDE) 46 47 #define SDRAM_ALL_VAL 0xf00 48 49 #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ 50 #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 51 52 #define MPCTL0_VAL 0x1ef15d5 53 54 #define SPCTL0_VAL 0x043a1c09 55 56 #define CSCR_VAL 0x33f08107 57 58 #define PCDR0_VAL 0x120470c3 59 #define PCDR1_VAL 0x03030303 60 #define PCCR0_VAL 0xffffffff 61 #define PCCR1_VAL 0xfffffffc 62 63 #define AIPI1_PSR0_VAL 0x20040304 64 #define AIPI1_PSR1_VAL 0xdffbfcfb 65 #define AIPI2_PSR0_VAL 0x07ffc200 66 #define AIPI2_PSR1_VAL 0xffffffff 67 68 /* 69 * Memory Info 70 */ 71 /* malloc() len */ 72 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) 73 /* memtest start address */ 74 #define CONFIG_SYS_MEMTEST_START 0xA0000000 75 #define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ 76 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 77 #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ 78 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ 79 80 /* 81 * Serial Driver info 82 */ 83 #define CONFIG_MXC_UART 84 #define CONFIG_MXC_UART_BASE UART1_BASE 85 86 /* 87 * Flash & Environment 88 */ 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_CFI 91 /* Use buffered writes (~10x faster) */ 92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 93 /* Use hardware sector protection */ 94 #define CONFIG_SYS_FLASH_PROTECTION 1 95 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 96 /* CS2 Base address */ 97 #define PHYS_FLASH_1 0xc0000000 98 /* Flash Base for U-Boot */ 99 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 100 #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ 101 CONFIG_SYS_FLASH_SECT_SZ) 102 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 103 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ 104 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 105 /* Address and size of Redundant Environment Sector */ 106 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 107 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 108 109 /* 110 * Ethernet 111 */ 112 #define CONFIG_FEC_MXC 113 #define CONFIG_FEC_MXC_PHYADDR 0x1f 114 #define CONFIG_MII 115 116 /* 117 * MTD 118 */ 119 #define CONFIG_FLASH_CFI_MTD 120 #define CONFIG_MTD_DEVICE 121 122 /* 123 * NAND 124 */ 125 #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 126 #define CONFIG_SYS_MAX_NAND_DEVICE 1 127 #define CONFIG_SYS_NAND_BASE 0xd8000000 128 #define CONFIG_JFFS2_NAND 129 #define CONFIG_MXC_NAND_HWECC 130 131 /* 132 * U-Boot general configuration 133 */ 134 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 135 /* Boot Argument Buffer Size */ 136 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 137 138 #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ 139 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 140 141 #define CONFIG_EXTRA_ENV_SETTINGS \ 142 "netdev=eth0\0" \ 143 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 144 "nfsroot=${serverip}:${rootpath}\0" \ 145 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 146 "addip=setenv bootargs ${bootargs} " \ 147 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 148 ":${hostname}:${netdev}:off panic=1\0" \ 149 "addtty=setenv bootargs ${bootargs}" \ 150 " console=ttymxc0,${baudrate}\0" \ 151 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 152 "addmisc=setenv bootargs ${bootargs}\0" \ 153 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ 154 "kernel_addr_r=a0800000\0" \ 155 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 156 "rootpath=/opt/eldk-4.2-arm/arm\0" \ 157 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 158 "run nfsargs addip addtty addmtd addmisc;" \ 159 "bootm\0" \ 160 "bootcmd=run net_nfs\0" \ 161 "load=tftp ${loadaddr} ${u-boot}\0" \ 162 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 163 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 164 " +${filesize};cp.b ${fileaddr} " \ 165 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 166 "upd=run load update\0" \ 167 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 168 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 169 170 /* additions for new relocation code, must be added to all boards */ 171 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 172 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 173 GENERATED_GBL_DATA_SIZE) 174 #endif /* __IMX27LITE_COMMON_CONFIG_H */ 175