1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2010 Heiko Schocher <hs@denx.de> 4 * 5 * based on: 6 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> 7 */ 8 9 #ifndef __IMX27LITE_COMMON_CONFIG_H 10 #define __IMX27LITE_COMMON_CONFIG_H 11 12 /* 13 * SoC Configuration 14 */ 15 #define CONFIG_MX27 16 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ 17 18 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 19 #define CONFIG_SETUP_MEMORY_TAGS 1 20 #define CONFIG_INITRD_TAG 1 21 22 /* 23 * Lowlevel configuration 24 */ 25 #define SDRAM_ESDCFG_REGISTER_VAL(cas) \ 26 (ESDCFG_TRC(10) | \ 27 ESDCFG_TRCD(3) | \ 28 ESDCFG_TCAS(cas) | \ 29 ESDCFG_TRRD(1) | \ 30 ESDCFG_TRAS(5) | \ 31 ESDCFG_TWR | \ 32 ESDCFG_TMRD(2) | \ 33 ESDCFG_TRP(2) | \ 34 ESDCFG_TXP(3)) 35 36 #define SDRAM_ESDCTL_REGISTER_VAL \ 37 (ESDCTL_PRCT(0) | \ 38 ESDCTL_BL | \ 39 ESDCTL_PWDT(0) | \ 40 ESDCTL_SREFR(3) | \ 41 ESDCTL_DSIZ_32 | \ 42 ESDCTL_COL10 | \ 43 ESDCTL_ROW13 | \ 44 ESDCTL_SDE) 45 46 #define SDRAM_ALL_VAL 0xf00 47 48 #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ 49 #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 50 51 #define MPCTL0_VAL 0x1ef15d5 52 53 #define SPCTL0_VAL 0x043a1c09 54 55 #define CSCR_VAL 0x33f08107 56 57 #define PCDR0_VAL 0x120470c3 58 #define PCDR1_VAL 0x03030303 59 #define PCCR0_VAL 0xffffffff 60 #define PCCR1_VAL 0xfffffffc 61 62 #define AIPI1_PSR0_VAL 0x20040304 63 #define AIPI1_PSR1_VAL 0xdffbfcfb 64 #define AIPI2_PSR0_VAL 0x07ffc200 65 #define AIPI2_PSR1_VAL 0xffffffff 66 67 /* 68 * Memory Info 69 */ 70 /* malloc() len */ 71 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) 72 /* memtest start address */ 73 #define CONFIG_SYS_MEMTEST_START 0xA0000000 74 #define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ 75 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 76 #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ 77 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ 78 79 /* 80 * Serial Driver info 81 */ 82 #define CONFIG_MXC_UART 83 #define CONFIG_MXC_UART_BASE UART1_BASE 84 85 /* 86 * Flash & Environment 87 */ 88 #define CONFIG_FLASH_CFI_DRIVER 89 #define CONFIG_SYS_FLASH_CFI 90 /* Use buffered writes (~10x faster) */ 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 92 /* Use hardware sector protection */ 93 #define CONFIG_SYS_FLASH_PROTECTION 1 94 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 95 /* CS2 Base address */ 96 #define PHYS_FLASH_1 0xc0000000 97 /* Flash Base for U-Boot */ 98 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 99 #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ 100 CONFIG_SYS_FLASH_SECT_SZ) 101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 102 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ 103 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 104 /* Address and size of Redundant Environment Sector */ 105 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 106 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 107 108 /* 109 * Ethernet 110 */ 111 #define CONFIG_FEC_MXC 112 #define CONFIG_FEC_MXC_PHYADDR 0x1f 113 #define CONFIG_MII 114 115 /* 116 * MTD 117 */ 118 #define CONFIG_FLASH_CFI_MTD 119 120 /* 121 * NAND 122 */ 123 #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 124 #define CONFIG_SYS_MAX_NAND_DEVICE 1 125 #define CONFIG_SYS_NAND_BASE 0xd8000000 126 #define CONFIG_JFFS2_NAND 127 #define CONFIG_MXC_NAND_HWECC 128 129 /* 130 * U-Boot general configuration 131 */ 132 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 133 /* Boot Argument Buffer Size */ 134 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 135 136 #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ 137 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 138 139 #define CONFIG_EXTRA_ENV_SETTINGS \ 140 "netdev=eth0\0" \ 141 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 142 "nfsroot=${serverip}:${rootpath}\0" \ 143 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 144 "addip=setenv bootargs ${bootargs} " \ 145 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 146 ":${hostname}:${netdev}:off panic=1\0" \ 147 "addtty=setenv bootargs ${bootargs}" \ 148 " console=ttymxc0,${baudrate}\0" \ 149 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 150 "addmisc=setenv bootargs ${bootargs}\0" \ 151 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ 152 "kernel_addr_r=a0800000\0" \ 153 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ 154 "rootpath=/opt/eldk-4.2-arm/arm\0" \ 155 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 156 "run nfsargs addip addtty addmtd addmisc;" \ 157 "bootm\0" \ 158 "bootcmd=run net_nfs\0" \ 159 "load=tftp ${loadaddr} ${u-boot}\0" \ 160 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 161 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 162 " +${filesize};cp.b ${fileaddr} " \ 163 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 164 "upd=run load update\0" \ 165 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 166 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 167 168 /* additions for new relocation code, must be added to all boards */ 169 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 170 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 171 GENERATED_GBL_DATA_SIZE) 172 #endif /* __IMX27LITE_COMMON_CONFIG_H */ 173