1 /*
2  * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
3  *
4  * based on:
5  * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __IMX27LITE_COMMON_CONFIG_H
11 #define __IMX27LITE_COMMON_CONFIG_H
12 
13 /*
14  * SoC Configuration
15  */
16 #define CONFIG_MX27
17 #define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
18 
19 #define CONFIG_DISPLAY_BOARDINFO
20 #define CONFIG_DISPLAY_CPUINFO
21 
22 #define CONFIG_SYS_TEXT_BASE		0xc0000000
23 
24 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
25 #define CONFIG_SETUP_MEMORY_TAGS	1
26 #define CONFIG_INITRD_TAG		1
27 
28 /*
29  * Lowlevel configuration
30  */
31 #define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
32 		(ESDCFG_TRC(10) |	\
33 		ESDCFG_TRCD(3) |	\
34 		ESDCFG_TCAS(cas) |	\
35 		ESDCFG_TRRD(1) |	\
36 		ESDCFG_TRAS(5) |	\
37 		ESDCFG_TWR |		\
38 		ESDCFG_TMRD(2) |	\
39 		ESDCFG_TRP(2) |		\
40 		ESDCFG_TXP(3))
41 
42 #define SDRAM_ESDCTL_REGISTER_VAL	\
43 		(ESDCTL_PRCT(0) |	\
44 		 ESDCTL_BL |		\
45 		 ESDCTL_PWDT(0) |	\
46 		 ESDCTL_SREFR(3) |	\
47 		 ESDCTL_DSIZ_32 |	\
48 		 ESDCTL_COL10 |		\
49 		 ESDCTL_ROW13 |		\
50 		 ESDCTL_SDE)
51 
52 #define SDRAM_ALL_VAL		0xf00
53 
54 #define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
55 #define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
56 
57 #define MPCTL0_VAL	0x1ef15d5
58 
59 #define SPCTL0_VAL	0x043a1c09
60 
61 #define CSCR_VAL	0x33f08107
62 
63 #define PCDR0_VAL	0x120470c3
64 #define PCDR1_VAL	0x03030303
65 #define PCCR0_VAL	0xffffffff
66 #define PCCR1_VAL	0xfffffffc
67 
68 #define AIPI1_PSR0_VAL	0x20040304
69 #define AIPI1_PSR1_VAL	0xdffbfcfb
70 #define AIPI2_PSR0_VAL	0x07ffc200
71 #define AIPI2_PSR1_VAL	0xffffffff
72 
73 /*
74  * Memory Info
75  */
76 /* malloc() len */
77 #define CONFIG_SYS_MALLOC_LEN		(0x10000 + 512 * 1024)
78 /* memtest start address */
79 #define CONFIG_SYS_MEMTEST_START	0xA0000000
80 #define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
81 #define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
82 #define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
83 #define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
84 
85 /*
86  * Serial Driver info
87  */
88 #define CONFIG_MXC_UART
89 #define CONFIG_MXC_UART_BASE	UART1_BASE
90 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
91 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
92 
93 /*
94  * Flash & Environment
95  */
96 #define CONFIG_ENV_IS_IN_FLASH
97 #define CONFIG_FLASH_CFI_DRIVER
98 #define CONFIG_SYS_FLASH_CFI
99 /* Use buffered writes (~10x faster) */
100 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
101 /* Use hardware sector protection */
102 #define CONFIG_SYS_FLASH_PROTECTION		1
103 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
104 /* CS2 Base address */
105 #define PHYS_FLASH_1			0xc0000000
106 /* Flash Base for U-Boot */
107 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
108 #define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
109 		CONFIG_SYS_FLASH_SECT_SZ)
110 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
111 #define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
112 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
113 /* Address and size of Redundant Environment Sector	*/
114 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
115 #define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
116 
117 /*
118  * Ethernet
119  */
120 #define CONFIG_FEC_MXC
121 #define CONFIG_FEC_MXC_PHYADDR		0x1f
122 #define CONFIG_MII
123 
124 /*
125  * MTD
126  */
127 #define CONFIG_FLASH_CFI_MTD
128 #define CONFIG_MTD_DEVICE
129 
130 /*
131  * NAND
132  */
133 #define CONFIG_NAND_MXC
134 #define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
135 #define CONFIG_SYS_MAX_NAND_DEVICE	1
136 #define CONFIG_SYS_NAND_BASE		0xd8000000
137 #define CONFIG_JFFS2_NAND
138 #define CONFIG_MXC_NAND_HWECC
139 
140 /*
141  * SD/MMC
142  */
143 #define CONFIG_MMC
144 #define CONFIG_GENERIC_MMC
145 #define CONFIG_MXC_MMC
146 #define CONFIG_DOS_PARTITION
147 
148 /*
149  * GPIO
150  */
151 #define CONFIG_MXC_GPIO
152 
153 /*
154  * MTD partitions
155  */
156 #define CONFIG_CMD_MTDPARTS
157 
158 /*
159  * U-Boot general configuration
160  */
161 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
162 /* Print buffer sz */
163 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
164 		sizeof(CONFIG_SYS_PROMPT) + 16)
165 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
166 /* Boot Argument Buffer Size */
167 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
168 #define CONFIG_CMDLINE_EDITING
169 #define CONFIG_SYS_LONGHELP
170 
171 /*
172  * U-Boot commands
173  */
174 #include <config_cmd_default.h>
175 #define CONFIG_CMD_ASKENV
176 #define CONFIG_CMD_CACHE
177 #define CONFIG_CMD_DHCP
178 #define CONFIG_CMD_DIAG
179 #define CONFIG_CMD_FAT
180 #define CONFIG_CMD_JFFS2
181 #define CONFIG_CMD_MII
182 #define CONFIG_CMD_MMC
183 #define CONFIG_CMD_NAND
184 #define CONFIG_CMD_PING
185 
186 #define CONFIG_BOOTDELAY	5
187 
188 #define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
189 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
190 
191 #define	CONFIG_EXTRA_ENV_SETTINGS					\
192 	"netdev=eth0\0"							\
193 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
194 		"nfsroot=${serverip}:${rootpath}\0"			\
195 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
196 	"addip=setenv bootargs ${bootargs} "				\
197 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
198 		":${hostname}:${netdev}:off panic=1\0"			\
199 	"addtty=setenv bootargs ${bootargs}"				\
200 		" console=ttymxc0,${baudrate}\0"			\
201 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
202 	"addmisc=setenv bootargs ${bootargs}\0"				\
203 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
204 	"kernel_addr_r=a0800000\0"					\
205 	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
206 	"rootpath=/opt/eldk-4.2-arm/arm\0"				\
207 	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
208 		"run nfsargs addip addtty addmtd addmisc;"		\
209 		"bootm\0"						\
210 	"bootcmd=run net_nfs\0"						\
211 	"load=tftp ${loadaddr} ${u-boot}\0"				\
212 	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
213 		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
214 		" +${filesize};cp.b ${fileaddr} "			\
215 		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
216 	"upd=run load update\0"						\
217 	"mtdids=" MTDIDS_DEFAULT "\0"					\
218 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
219 
220 /* additions for new relocation code, must be added to all boards */
221 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
222 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
223 					GENERATED_GBL_DATA_SIZE)
224 #endif /* __IMX27LITE_COMMON_CONFIG_H */
225