1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 * 6 * Based on: 7 * Copyright (c) 2011 IDS GmbH, Germany 8 * Sergej Stepanov <ste@ids.de> 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_MPC831x 18 #define CONFIG_MPC8313 19 20 #define CONFIG_FSL_ELBC 21 22 #define CONFIG_BOOT_RETRY_TIME 900 23 #define CONFIG_BOOT_RETRY_MIN 30 24 #define CONFIG_RESET_TO_RETRY 25 26 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 27 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 28 29 #define CONFIG_SYS_IMMR 0xF0000000 30 31 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 32 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 33 34 /* 35 * Hardware Reset Configuration Word 36 * if CLKIN is 66.000MHz, then 37 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz 38 */ 39 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ 40 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 41 HRCWL_CSB_TO_CLKIN_2X1 |\ 42 HRCWL_CORE_TO_CSB_2X1) 43 44 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ 45 HRCWH_CORE_ENABLE |\ 46 HRCWH_FROM_0XFFF00100 |\ 47 HRCWH_BOOTSEQ_DISABLE |\ 48 HRCWH_SW_WATCHDOG_DISABLE |\ 49 HRCWH_ROM_LOC_LOCAL_8BIT |\ 50 HRCWH_RL_EXT_LEGACY |\ 51 HRCWH_TSEC1M_IN_MII |\ 52 HRCWH_TSEC2M_IN_MII |\ 53 HRCWH_BIG_ENDIAN) 54 55 #define CONFIG_SYS_SICRH 0x00000000 56 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) 57 58 #define CONFIG_HWCONFIG 59 60 #define CONFIG_SYS_HID0_INIT 0x000000000 61 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ 62 HID0_ENABLE_INSTRUCTION_CACHE |\ 63 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) 64 65 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) 66 67 /* 68 * Definitions for initial stack pointer and data area (in DCACHE ) 69 */ 70 #define CONFIG_SYS_INIT_RAM_LOCK 71 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ 73 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 74 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 75 - CONFIG_SYS_GBL_DATA_SIZE) 76 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 77 78 /* 79 * Local Bus LCRR and LBCR regs 80 */ 81 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 82 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 83 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ 84 (0xFF << LBCR_BMT_SHIFT) |\ 85 0xF) 86 87 #define CONFIG_SYS_LBC_MRTPR 0x20000000 88 89 /* 90 * Internal Definitions 91 */ 92 /* 93 * DDR Setup 94 */ 95 #define CONFIG_SYS_DDR_BASE 0x00000000 96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 97 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 98 99 /* 100 * Manually set up DDR parameters, 101 * as this board has not the SPD connected to I2C. 102 */ 103 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 104 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ 105 0x00010000 |\ 106 CSCONFIG_ROW_BIT_13 |\ 107 CSCONFIG_COL_BIT_10) 108 109 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ 110 CSCONFIG_BANK_BIT_3) 111 112 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ 113 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ 114 (3 << TIMING_CFG0_WRT_SHIFT) |\ 115 (3 << TIMING_CFG0_RRT_SHIFT) |\ 116 (3 << TIMING_CFG0_WWT_SHIFT) |\ 117 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ 118 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ 119 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 120 (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 121 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ 122 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ 123 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ 124 (7 << TIMING_CFG1_CASLAT_SHIFT) |\ 125 (4 << TIMING_CFG1_REFREC_SHIFT) |\ 126 (4 << TIMING_CFG1_WRREC_SHIFT) |\ 127 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ 128 (2 << TIMING_CFG1_WRTORD_SHIFT)) 129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ 130 (5 << TIMING_CFG2_CPO_SHIFT) |\ 131 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ 132 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ 133 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ 134 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ 135 (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 136 137 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ 138 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 139 140 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ 141 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ 142 SDRAM_CFG_DBW_32 |\ 143 SDRAM_CFG_SDRAM_TYPE_DDR2) 144 145 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 146 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ 147 (0x0242 << SDRAM_MODE_SD_SHIFT)) 148 #define CONFIG_SYS_DDR_MODE_2 0x00000000 149 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 150 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ 151 DDRCDR_PZ_NOMZ |\ 152 DDRCDR_NZ_NOMZ |\ 153 DDRCDR_ODT |\ 154 DDRCDR_M_ODR |\ 155 DDRCDR_Q_DRN) 156 157 /* 158 * on-board devices 159 */ 160 #define CONFIG_TSEC1 161 #define CONFIG_TSEC2 162 #define CONFIG_HARD_SPI 163 164 /* 165 * NOR FLASH setup 166 */ 167 #define CONFIG_SYS_FLASH_CFI 168 #define CONFIG_FLASH_CFI_DRIVER 169 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 170 #define CONFIG_FLASH_SHOW_PROGRESS 50 171 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 172 173 #define CONFIG_SYS_FLASH_BASE 0xFF800000 174 #define CONFIG_SYS_FLASH_SIZE 8 175 #define CONFIG_SYS_FLASH_PROTECTION 176 177 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 178 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 179 180 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 181 BR_PS_8 |\ 182 BR_MS_GPCM |\ 183 BR_V) 184 185 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 186 OR_GPCM_SCY_10 |\ 187 OR_GPCM_EHTR |\ 188 OR_GPCM_TRLX |\ 189 OR_GPCM_CSNT |\ 190 OR_GPCM_EAD) 191 #define CONFIG_SYS_MAX_FLASH_BANKS 1 192 #define CONFIG_SYS_MAX_FLASH_SECT 128 193 194 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 196 197 /* 198 * NAND FLASH setup 199 */ 200 #define CONFIG_SYS_NAND_BASE 0xE1000000 201 #define CONFIG_SYS_MAX_NAND_DEVICE 1 202 #define CONFIG_SYS_NAND_MAX_CHIPS 1 203 #define CONFIG_NAND_FSL_ELBC 204 #define CONFIG_SYS_NAND_PAGE_SIZE (2048) 205 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 206 #define NAND_CACHE_PAGES 64 207 208 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 209 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E 210 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 211 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 212 213 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ 214 (2<<BR_DECC_SHIFT) |\ 215 BR_PS_8 |\ 216 BR_MS_FCM |\ 217 BR_V) 218 219 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ 220 OR_FCM_PGS |\ 221 OR_FCM_CSCT |\ 222 OR_FCM_CST |\ 223 OR_FCM_CHT |\ 224 OR_FCM_SCY_4 |\ 225 OR_FCM_TRLX |\ 226 OR_FCM_EHTR |\ 227 OR_FCM_RST) 228 229 /* 230 * MRAM setup 231 */ 232 #define CONFIG_SYS_MRAM_BASE 0xE2000000 233 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ 234 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE 235 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ 236 237 #define CONFIG_SYS_OR_TIMING_MRAM 238 239 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ 240 BR_PS_8 |\ 241 BR_MS_GPCM |\ 242 BR_V) 243 244 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 245 246 /* 247 * CPLD setup 248 */ 249 #define CONFIG_SYS_CPLD_BASE 0xE3000000 250 #define CONFIG_SYS_CPLD_SIZE 0x8000 251 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE 252 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E 253 254 #define CONFIG_SYS_OR_TIMING_MRAM 255 256 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ 257 BR_PS_8 |\ 258 BR_MS_GPCM |\ 259 BR_V) 260 261 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 262 263 /* 264 * HW-Watchdog 265 */ 266 #define CONFIG_WATCHDOG 1 267 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF 268 269 /* 270 * I2C setup 271 */ 272 #define CONFIG_SYS_I2C 273 #define CONFIG_SYS_I2C_FSL 274 #define CONFIG_SYS_FSL_I2C_SPEED 400000 275 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 276 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 277 #define CONFIG_RTC_PCF8563 278 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 279 280 /* 281 * SPI setup 282 */ 283 #ifdef CONFIG_HARD_SPI 284 #define CONFIG_SYS_GPIO1_PRELIM 285 #define CONFIG_SYS_GPIO1_DIR 0x00000001 286 #define CONFIG_SYS_GPIO1_DAT 0x00000001 287 #endif 288 289 /* 290 * Ethernet setup 291 */ 292 #ifdef CONFIG_TSEC1 293 #define CONFIG_HAS_ETH0 294 #define CONFIG_TSEC1_NAME "TSEC0" 295 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 296 #define TSEC1_PHY_ADDR 0x1 297 #define TSEC1_FLAGS TSEC_GIGABIT 298 #define TSEC1_PHYIDX 0 299 #endif 300 301 #ifdef CONFIG_TSEC2 302 #define CONFIG_HAS_ETH1 303 #define CONFIG_TSEC2_NAME "TSEC1" 304 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 305 #define TSEC2_PHY_ADDR 0x3 306 #define TSEC2_FLAGS TSEC_GIGABIT 307 #define TSEC2_PHYIDX 0 308 #endif 309 #define CONFIG_ETHPRIME "TSEC1" 310 311 /* 312 * Serial Port 313 */ 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 317 #define CONFIG_SYS_BAUDRATE_TABLE \ 318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 321 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 322 323 #define CONFIG_HAS_FSL_DR_USB 324 #define CONFIG_SYS_SCCR_USBDRCM 3 325 326 /* 327 * BAT's 328 */ 329 #define CONFIG_HIGH_BATS 330 331 /* DDR @ 0x00000000 */ 332 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ 333 BATL_PP_10) 334 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ 335 BATU_BL_256M |\ 336 BATU_VS |\ 337 BATU_VP) 338 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 339 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 340 341 /* Initial RAM @ 0xFD000000 */ 342 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ 343 BATL_PP_10 |\ 344 BATL_GUARDEDSTORAGE) 345 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ 346 BATU_BL_256K |\ 347 BATU_VS |\ 348 BATU_VP) 349 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 350 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 351 352 /* FLASH @ 0xFF800000 */ 353 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ 354 BATL_PP_10 |\ 355 BATL_GUARDEDSTORAGE) 356 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ 357 BATU_BL_8M |\ 358 BATU_VS |\ 359 BATU_VP) 360 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ 361 BATL_PP_10 |\ 362 BATL_CACHEINHIBIT |\ 363 BATL_GUARDEDSTORAGE) 364 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 365 366 #define CONFIG_SYS_IBAT3L (0) 367 #define CONFIG_SYS_IBAT3U (0) 368 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 369 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 370 371 #define CONFIG_SYS_IBAT4L (0) 372 #define CONFIG_SYS_IBAT4U (0) 373 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 374 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 375 376 /* IMMRBAR @ 0xF0000000 */ 377 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ 378 BATL_PP_10 |\ 379 BATL_CACHEINHIBIT |\ 380 BATL_GUARDEDSTORAGE) 381 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ 382 BATU_BL_128M |\ 383 BATU_VS |\ 384 BATU_VP) 385 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 386 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 387 388 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ 389 #define CONFIG_SYS_IBAT6L (0xE0000000 |\ 390 BATL_PP_10 |\ 391 BATL_GUARDEDSTORAGE) 392 #define CONFIG_SYS_IBAT6U (0xE0000000 |\ 393 BATU_BL_256M |\ 394 BATU_VS |\ 395 BATU_VP) 396 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 397 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 398 399 #define CONFIG_SYS_IBAT7L (0) 400 #define CONFIG_SYS_IBAT7U (0) 401 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 402 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 403 404 /* 405 * U-Boot environment setup 406 */ 407 #define CONFIG_BOOTP_BOOTFILESIZE 408 409 /* 410 * The reserved memory 411 */ 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 413 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 414 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) 415 416 /* 417 * Environment Configuration 418 */ 419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 420 + CONFIG_SYS_MONITOR_LEN) 421 #define CONFIG_ENV_SIZE 0x20000 422 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 423 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 424 425 #define CONFIG_NETDEV eth1 426 #define CONFIG_HOSTNAME "ids8313" 427 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" 428 #define CONFIG_BOOTFILE "ids8313/uImage" 429 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" 430 #define CONFIG_FDTFILE "ids8313/ids8313.dtb" 431 #define CONFIG_LOADADDR 0x400000 432 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" 433 434 /* Initial Memory map for Linux*/ 435 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 436 437 /* 438 * Miscellaneous configurable options 439 */ 440 #define CONFIG_SYS_CBSIZE 1024 441 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 442 443 #define CONFIG_SYS_MEMTEST_START 0x00001000 444 #define CONFIG_SYS_MEMTEST_END 0x00C00000 445 446 #define CONFIG_SYS_LOAD_ADDR 0x100000 447 #define CONFIG_LOADS_ECHO 448 #define CONFIG_TIMESTAMP 449 #define CONFIG_PREBOOT "echo;" \ 450 "echo Type \\\"run nfsboot\\\" " \ 451 "to mount root filesystem over NFS;echo" 452 #define CONFIG_BOOTCOMMAND "run boot_cramfs" 453 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 454 455 #define CONFIG_JFFS2_NAND 456 #define CONFIG_JFFS2_DEV "0" 457 458 /* mtdparts command line support */ 459 #define CONFIG_FLASH_CFI_MTD 460 461 #define CONFIG_EXTRA_ENV_SETTINGS \ 462 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 463 "ethprime=TSEC1\0" \ 464 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 465 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ 466 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 467 " +${filesize}; " \ 468 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 469 " +${filesize}; " \ 470 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 471 " ${filesize}; " \ 472 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 473 " +${filesize}; " \ 474 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 475 " ${filesize}\0" \ 476 "console=ttyS0\0" \ 477 "fdtaddr=0x780000\0" \ 478 "kernel_addr=ff800000\0" \ 479 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ 480 "setbootargs=setenv bootargs " \ 481 "root=${rootdev} rw console=${console}," \ 482 "${baudrate} ${othbootargs}\0" \ 483 "setipargs=setenv bootargs root=${rootdev} rw " \ 484 "nfsroot=${serverip}:${rootpath} " \ 485 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 486 "${netmask}:${hostname}:${netdev}:off " \ 487 "console=${console},${baudrate} ${othbootargs}\0" \ 488 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 489 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 490 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 491 "\0" 492 493 #define CONFIG_NFSBOOTCOMMAND \ 494 "setenv rootdev /dev/nfs;" \ 495 "run setipargs;run addmtd;" \ 496 "tftp ${loadaddr} ${bootfile};" \ 497 "tftp ${fdtaddr} ${fdtfile};" \ 498 "fdt addr ${fdtaddr};" \ 499 "bootm ${loadaddr} - ${fdtaddr}" 500 501 /* UBI Support */ 502 503 #endif /* __CONFIG_H */ 504