1 /* 2 * (C) Copyright 2013 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * Based on: 6 * Copyright (c) 2011 IDS GmbH, Germany 7 * Sergej Stepanov <ste@ids.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_MPC831x 19 #define CONFIG_MPC8313 20 #define CONFIG_IDS8313 21 22 #define CONFIG_SYS_GENERIC_BOARD 23 24 #define CONFIG_FSL_ELBC 25 26 #define CONFIG_MISC_INIT_R 27 28 #define CONFIG_AUTOBOOT_KEYED 29 #define CONFIG_AUTOBOOT_PROMPT \ 30 "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY 31 #define CONFIG_AUTOBOOT_DELAY_STR "ids" 32 #define CONFIG_BOOT_RETRY_TIME 900 33 #define CONFIG_BOOT_RETRY_MIN 30 34 #define CONFIG_BOOTDELAY 1 35 #define CONFIG_RESET_TO_RETRY 36 37 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 38 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 39 40 #define CONFIG_SYS_IMMR 0xF0000000 41 42 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 43 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 44 45 /* 46 * Hardware Reset Configuration Word 47 * if CLKIN is 66.000MHz, then 48 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz 49 */ 50 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ 51 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 52 HRCWL_CSB_TO_CLKIN_2X1 |\ 53 HRCWL_CORE_TO_CSB_2X1) 54 55 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ 56 HRCWH_CORE_ENABLE |\ 57 HRCWH_FROM_0XFFF00100 |\ 58 HRCWH_BOOTSEQ_DISABLE |\ 59 HRCWH_SW_WATCHDOG_DISABLE |\ 60 HRCWH_ROM_LOC_LOCAL_8BIT |\ 61 HRCWH_RL_EXT_LEGACY |\ 62 HRCWH_TSEC1M_IN_MII |\ 63 HRCWH_TSEC2M_IN_MII |\ 64 HRCWH_BIG_ENDIAN) 65 66 #define CONFIG_SYS_SICRH 0x00000000 67 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) 68 69 #define CONFIG_HWCONFIG 70 71 #define CONFIG_SYS_HID0_INIT 0x000000000 72 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ 73 HID0_ENABLE_INSTRUCTION_CACHE |\ 74 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) 75 76 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) 77 78 /* 79 * Definitions for initial stack pointer and data area (in DCACHE ) 80 */ 81 #define CONFIG_SYS_INIT_RAM_LOCK 82 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 83 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ 84 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 85 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 86 - CONFIG_SYS_GBL_DATA_SIZE) 87 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 88 89 /* 90 * Local Bus LCRR and LBCR regs 91 */ 92 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 93 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 94 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ 95 (0xFF << LBCR_BMT_SHIFT) |\ 96 0xF) 97 98 #define CONFIG_SYS_LBC_MRTPR 0x20000000 99 100 /* 101 * Internal Definitions 102 */ 103 /* 104 * DDR Setup 105 */ 106 #define CONFIG_SYS_DDR_BASE 0x00000000 107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 109 110 /* 111 * Manually set up DDR parameters, 112 * as this board has not the SPD connected to I2C. 113 */ 114 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 115 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ 116 0x00010000 |\ 117 CSCONFIG_ROW_BIT_13 |\ 118 CSCONFIG_COL_BIT_10) 119 120 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ 121 CSCONFIG_BANK_BIT_3) 122 123 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ 124 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ 125 (3 << TIMING_CFG0_WRT_SHIFT) |\ 126 (3 << TIMING_CFG0_RRT_SHIFT) |\ 127 (3 << TIMING_CFG0_WWT_SHIFT) |\ 128 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ 129 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ 130 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 131 (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 132 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ 133 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ 134 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ 135 (7 << TIMING_CFG1_CASLAT_SHIFT) |\ 136 (4 << TIMING_CFG1_REFREC_SHIFT) |\ 137 (4 << TIMING_CFG1_WRREC_SHIFT) |\ 138 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ 139 (2 << TIMING_CFG1_WRTORD_SHIFT)) 140 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ 141 (5 << TIMING_CFG2_CPO_SHIFT) |\ 142 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ 143 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ 144 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ 145 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ 146 (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 147 148 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ 149 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 150 151 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ 152 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ 153 SDRAM_CFG_DBW_32 |\ 154 SDRAM_CFG_SDRAM_TYPE_DDR2) 155 156 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 157 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ 158 (0x0242 << SDRAM_MODE_SD_SHIFT)) 159 #define CONFIG_SYS_DDR_MODE_2 0x00000000 160 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 161 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ 162 DDRCDR_PZ_NOMZ |\ 163 DDRCDR_NZ_NOMZ |\ 164 DDRCDR_ODT |\ 165 DDRCDR_M_ODR |\ 166 DDRCDR_Q_DRN) 167 168 /* 169 * on-board devices 170 */ 171 #define CONFIG_TSEC1 172 #define CONFIG_TSEC2 173 #define CONFIG_TSEC_ENET 174 #define CONFIG_NET_MULTI 175 #define CONFIG_HARD_SPI 176 #define CONFIG_HARD_I2C 177 178 /* 179 * NOR FLASH setup 180 */ 181 #define CONFIG_SYS_FLASH_CFI 182 #define CONFIG_FLASH_CFI_DRIVER 183 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 184 #define CONFIG_FLASH_SHOW_PROGRESS 50 185 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 186 187 #define CONFIG_SYS_FLASH_BASE 0xFF800000 188 #define CONFIG_SYS_FLASH_SIZE 8 189 #define CONFIG_SYS_FLASH_PROTECTION 190 191 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 192 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 193 194 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 195 BR_PS_8 |\ 196 BR_MS_GPCM |\ 197 BR_V) 198 199 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 200 OR_GPCM_SCY_10 |\ 201 OR_GPCM_EHTR |\ 202 OR_GPCM_TRLX |\ 203 OR_GPCM_CSNT |\ 204 OR_GPCM_EAD) 205 #define CONFIG_SYS_MAX_FLASH_BANKS 1 206 #define CONFIG_SYS_MAX_FLASH_SECT 128 207 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 210 211 /* 212 * NAND FLASH setup 213 */ 214 #define CONFIG_SYS_NAND_BASE 0xE1000000 215 #define CONFIG_SYS_MAX_NAND_DEVICE 1 216 #define CONFIG_SYS_NAND_MAX_CHIPS 1 217 #define CONFIG_MTD_NAND_VERIFY_WRITE 218 #define CONFIG_NAND_FSL_ELBC 219 #define CONFIG_SYS_NAND_PAGE_SIZE (2048) 220 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 221 #define NAND_CACHE_PAGES 64 222 223 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 224 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E 225 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 226 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 227 228 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ 229 (2<<BR_DECC_SHIFT) |\ 230 BR_PS_8 |\ 231 BR_MS_FCM |\ 232 BR_V) 233 234 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ 235 OR_FCM_PGS |\ 236 OR_FCM_CSCT |\ 237 OR_FCM_CST |\ 238 OR_FCM_CHT |\ 239 OR_FCM_SCY_4 |\ 240 OR_FCM_TRLX |\ 241 OR_FCM_EHTR |\ 242 OR_FCM_RST) 243 244 /* 245 * MRAM setup 246 */ 247 #define CONFIG_SYS_MRAM_BASE 0xE2000000 248 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ 249 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE 250 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ 251 252 #define CONFIG_SYS_OR_TIMING_MRAM 253 254 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ 255 BR_PS_8 |\ 256 BR_MS_GPCM |\ 257 BR_V) 258 259 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 260 261 /* 262 * CPLD setup 263 */ 264 #define CONFIG_SYS_CPLD_BASE 0xE3000000 265 #define CONFIG_SYS_CPLD_SIZE 0x8000 266 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE 267 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E 268 269 #define CONFIG_SYS_OR_TIMING_MRAM 270 271 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ 272 BR_PS_8 |\ 273 BR_MS_GPCM |\ 274 BR_V) 275 276 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 277 278 /* 279 * HW-Watchdog 280 */ 281 #define CONFIG_WATCHDOG 1 282 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF 283 284 /* 285 * I2C setup 286 */ 287 #define CONFIG_CMD_I2C 288 #define CONFIG_SYS_I2C 289 #define CONFIG_SYS_I2C_FSL 290 #define CONFIG_SYS_FSL_I2C_SPEED 400000 291 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 292 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 293 #define CONFIG_RTC_PCF8563 294 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 295 296 /* 297 * SPI setup 298 */ 299 #ifdef CONFIG_HARD_SPI 300 #define CONFIG_MPC8XXX_SPI 301 #define CONFIG_CMD_SPI 302 #define CONFIG_SYS_GPIO1_PRELIM 303 #define CONFIG_SYS_GPIO1_DIR 0x00000001 304 #define CONFIG_SYS_GPIO1_DAT 0x00000001 305 #endif 306 307 /* 308 * Ethernet setup 309 */ 310 #ifdef CONFIG_TSEC1 311 #define CONFIG_HAS_ETH0 312 #define CONFIG_TSEC1_NAME "TSEC0" 313 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 314 #define TSEC1_PHY_ADDR 0x1 315 #define TSEC1_FLAGS TSEC_GIGABIT 316 #define TSEC1_PHYIDX 0 317 #endif 318 319 #ifdef CONFIG_TSEC2 320 #define CONFIG_HAS_ETH1 321 #define CONFIG_TSEC2_NAME "TSEC1" 322 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 323 #define TSEC2_PHY_ADDR 0x3 324 #define TSEC2_FLAGS TSEC_GIGABIT 325 #define TSEC2_PHYIDX 0 326 #endif 327 #define CONFIG_ETHPRIME "TSEC1" 328 329 /* 330 * Serial Port 331 */ 332 #define CONFIG_CONS_INDEX 1 333 #define CONFIG_SYS_NS16550 334 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 337 #define CONFIG_SYS_BAUDRATE_TABLE \ 338 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 341 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 342 343 #define CONFIG_HAS_FSL_DR_USB 344 #define CONFIG_SYS_SCCR_USBDRCM 3 345 346 /* 347 * BAT's 348 */ 349 #define CONFIG_HIGH_BATS 350 351 /* DDR @ 0x00000000 */ 352 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ 353 BATL_PP_10) 354 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ 355 BATU_BL_256M |\ 356 BATU_VS |\ 357 BATU_VP) 358 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 359 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 360 361 /* Initial RAM @ 0xFD000000 */ 362 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ 363 BATL_PP_10 |\ 364 BATL_GUARDEDSTORAGE) 365 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ 366 BATU_BL_256K |\ 367 BATU_VS |\ 368 BATU_VP) 369 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 370 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 371 372 /* FLASH @ 0xFF800000 */ 373 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ 374 BATL_PP_10 |\ 375 BATL_GUARDEDSTORAGE) 376 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ 377 BATU_BL_8M |\ 378 BATU_VS |\ 379 BATU_VP) 380 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ 381 BATL_PP_10 |\ 382 BATL_CACHEINHIBIT |\ 383 BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 385 386 #define CONFIG_SYS_IBAT3L (0) 387 #define CONFIG_SYS_IBAT3U (0) 388 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 389 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 390 391 #define CONFIG_SYS_IBAT4L (0) 392 #define CONFIG_SYS_IBAT4U (0) 393 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 394 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 395 396 /* IMMRBAR @ 0xF0000000 */ 397 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ 398 BATL_PP_10 |\ 399 BATL_CACHEINHIBIT |\ 400 BATL_GUARDEDSTORAGE) 401 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ 402 BATU_BL_128M |\ 403 BATU_VS |\ 404 BATU_VP) 405 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 406 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 407 408 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ 409 #define CONFIG_SYS_IBAT6L (0xE0000000 |\ 410 BATL_PP_10 |\ 411 BATL_GUARDEDSTORAGE) 412 #define CONFIG_SYS_IBAT6U (0xE0000000 |\ 413 BATU_BL_256M |\ 414 BATU_VS |\ 415 BATU_VP) 416 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 417 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 418 419 #define CONFIG_SYS_IBAT7L (0) 420 #define CONFIG_SYS_IBAT7U (0) 421 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 422 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 423 424 /* 425 * U-Boot environment setup 426 */ 427 #include <config_cmd_default.h> 428 429 #define CONFIG_CMD_DHCP 430 #define CONFIG_CMD_PING 431 #define CONFIG_CMD_NFS 432 #define CONFIG_CMD_NAND 433 #define CONFIG_CMD_FLASH 434 #define CONFIG_CMD_SNTP 435 #define CONFIG_CMD_MII 436 #define CONFIG_CMD_DATE 437 #define CONFIG_CMDLINE_EDITING 438 #define CONFIG_CMD_EDITENV 439 #define CONFIG_CMD_JFFS2 440 #define CONFIG_BOOTP_SUBNETMASK 441 #define CONFIG_BOOTP_GATEWAY 442 #define CONFIG_BOOTP_HOSTNAME 443 #define CONFIG_BOOTP_BOOTPATH 444 #define CONFIG_BOOTP_BOOTFILESIZE 445 /* pass open firmware flat tree */ 446 #define CONFIG_OF_LIBFDT 447 #define CONFIG_OF_BOARD_SETUP 448 #define CONFIG_OF_STDOUT_VIA_ALIAS 449 450 /* 451 * The reserved memory 452 */ 453 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 454 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 455 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) 456 457 /* 458 * Environment Configuration 459 */ 460 #define CONFIG_ENV_IS_IN_FLASH 461 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 462 + CONFIG_SYS_MONITOR_LEN) 463 #define CONFIG_ENV_SIZE 0x20000 464 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 465 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 466 467 468 #define CONFIG_NETDEV eth1 469 #define CONFIG_HOSTNAME ids8313 470 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" 471 #define CONFIG_BOOTFILE "ids8313/uImage" 472 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" 473 #define CONFIG_FDTFILE "ids8313/ids8313.dtb" 474 #define CONFIG_LOADADDR 0x400000 475 #define CONFIG_CMD_ENV_FLAGS 476 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" 477 478 #define CONFIG_BAUDRATE 115200 479 480 /* Initial Memory map for Linux*/ 481 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 482 483 /* 484 * Miscellaneous configurable options 485 */ 486 #define CONFIG_SYS_LONGHELP 487 #define CONFIG_SYS_PROMPT "=> " 488 #define CONFIG_SYS_CBSIZE 1024 489 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 490 + sizeof(CONFIG_SYS_PROMPT)+16) 491 #define CONFIG_SYS_MAXARGS 16 492 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 493 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 494 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 495 496 #define CONFIG_SYS_MEMTEST_START 0x00001000 497 #define CONFIG_SYS_MEMTEST_END 0x00C00000 498 499 #define CONFIG_SYS_LOAD_ADDR 0x100000 500 #define CONFIG_MII 501 #define CONFIG_LOADS_ECHO 502 #define CONFIG_TIMESTAMP 503 #define CONFIG_PREBOOT "echo;" \ 504 "echo Type \\\"run nfsboot\\\" " \ 505 "to mount root filesystem over NFS;echo" 506 #undef CONFIG_BOOTARGS 507 #define CONFIG_BOOTCOMMAND "run boot_cramfs" 508 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 509 510 #define CONFIG_JFFS2_NAND 511 #define CONFIG_JFFS2_DEV "0" 512 513 /* mtdparts command line support */ 514 #define CONFIG_CMD_MTDPARTS 515 #define CONFIG_FLASH_CFI_MTD 516 #define CONFIG_MTD_DEVICE 517 #define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash" 518 #define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \ 519 "768k(BOOT-BIN)," \ 520 "128k(BOOT-ENV),128k(BOOT-REDENV);" \ 521 "e1000000.flash:-(ubi)" 522 523 #define CONFIG_EXTRA_ENV_SETTINGS \ 524 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 525 "ethprime=TSEC1\0" \ 526 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 527 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ 528 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 529 " +${filesize}; " \ 530 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 531 " +${filesize}; " \ 532 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 533 " ${filesize}; " \ 534 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 535 " +${filesize}; " \ 536 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 537 " ${filesize}\0" \ 538 "console=ttyS0\0" \ 539 "fdtaddr=0x780000\0" \ 540 "kernel_addr=ff800000\0" \ 541 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ 542 "setbootargs=setenv bootargs " \ 543 "root=${rootdev} rw console=${console}," \ 544 "${baudrate} ${othbootargs}\0" \ 545 "setipargs=setenv bootargs root=${rootdev} rw " \ 546 "nfsroot=${serverip}:${rootpath} " \ 547 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 548 "${netmask}:${hostname}:${netdev}:off " \ 549 "console=${console},${baudrate} ${othbootargs}\0" \ 550 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 551 "mtdids=" MTDIDS_DEFAULT "\0" \ 552 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 553 "\0" 554 555 #define CONFIG_NFSBOOTCOMMAND \ 556 "setenv rootdev /dev/nfs;" \ 557 "run setipargs;run addmtd;" \ 558 "tftp ${loadaddr} ${bootfile};" \ 559 "tftp ${fdtaddr} ${fdtfile};" \ 560 "fdt addr ${fdtaddr};" \ 561 "bootm ${loadaddr} - ${fdtaddr}" 562 563 /* UBI Support */ 564 #define CONFIG_CMD_NAND_TRIMFFS 565 #define CONFIG_CMD_UBI 566 #define CONFIG_CMD_UBIFS 567 #define CONFIG_RBTREE 568 #define CONFIG_LZO 569 #define CONFIG_MTD_PARTITIONS 570 571 /* bootcount support */ 572 #define CONFIG_BOOTCOUNT_LIMIT 573 #define CONFIG_BOOTCOUNT_I2C 574 #define CONFIG_BOOTCOUNT_ALEN 1 575 #define CONFIG_SYS_BOOTCOUNT_ADDR 0x9 576 577 #define CONFIG_VERSION_VARIABLE 578 579 #define CONFIG_FIT 580 #define CONFIG_FIT_SIGNATURE 581 #define CONFIG_IMAGE_FORMAT_LEGACY 582 #define CONFIG_CMD_FDT 583 #define CONFIG_CMD_HASH 584 #define CONFIG_RSA 585 #define CONFIG_SHA1 586 #define CONFIG_SHA256 587 588 #endif /* __CONFIG_H */ 589