1 /* 2 * (C) Copyright 2013 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * Based on: 6 * Copyright (c) 2011 IDS GmbH, Germany 7 * Sergej Stepanov <ste@ids.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_MPC831x 19 #define CONFIG_MPC8313 20 21 #define CONFIG_FSL_ELBC 22 23 #define CONFIG_MISC_INIT_R 24 25 #define CONFIG_BOOT_RETRY_TIME 900 26 #define CONFIG_BOOT_RETRY_MIN 30 27 #define CONFIG_RESET_TO_RETRY 28 29 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 30 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 31 32 #define CONFIG_SYS_IMMR 0xF0000000 33 34 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 35 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 36 37 /* 38 * Hardware Reset Configuration Word 39 * if CLKIN is 66.000MHz, then 40 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz 41 */ 42 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ 43 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 44 HRCWL_CSB_TO_CLKIN_2X1 |\ 45 HRCWL_CORE_TO_CSB_2X1) 46 47 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ 48 HRCWH_CORE_ENABLE |\ 49 HRCWH_FROM_0XFFF00100 |\ 50 HRCWH_BOOTSEQ_DISABLE |\ 51 HRCWH_SW_WATCHDOG_DISABLE |\ 52 HRCWH_ROM_LOC_LOCAL_8BIT |\ 53 HRCWH_RL_EXT_LEGACY |\ 54 HRCWH_TSEC1M_IN_MII |\ 55 HRCWH_TSEC2M_IN_MII |\ 56 HRCWH_BIG_ENDIAN) 57 58 #define CONFIG_SYS_SICRH 0x00000000 59 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) 60 61 #define CONFIG_HWCONFIG 62 63 #define CONFIG_SYS_HID0_INIT 0x000000000 64 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\ 65 HID0_ENABLE_INSTRUCTION_CACHE |\ 66 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT) 67 68 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000) 69 70 /* 71 * Definitions for initial stack pointer and data area (in DCACHE ) 72 */ 73 #define CONFIG_SYS_INIT_RAM_LOCK 74 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 75 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ 76 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 77 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 78 - CONFIG_SYS_GBL_DATA_SIZE) 79 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 80 81 /* 82 * Local Bus LCRR and LBCR regs 83 */ 84 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 85 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 86 #define CONFIG_SYS_LBC_LBCR (0x00040000 |\ 87 (0xFF << LBCR_BMT_SHIFT) |\ 88 0xF) 89 90 #define CONFIG_SYS_LBC_MRTPR 0x20000000 91 92 /* 93 * Internal Definitions 94 */ 95 /* 96 * DDR Setup 97 */ 98 #define CONFIG_SYS_DDR_BASE 0x00000000 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 100 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 101 102 /* 103 * Manually set up DDR parameters, 104 * as this board has not the SPD connected to I2C. 105 */ 106 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 107 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ 108 0x00010000 |\ 109 CSCONFIG_ROW_BIT_13 |\ 110 CSCONFIG_COL_BIT_10) 111 112 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ 113 CSCONFIG_BANK_BIT_3) 114 115 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ 116 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ 117 (3 << TIMING_CFG0_WRT_SHIFT) |\ 118 (3 << TIMING_CFG0_RRT_SHIFT) |\ 119 (3 << TIMING_CFG0_WWT_SHIFT) |\ 120 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ 121 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ 122 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 123 (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 124 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ 125 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ 126 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ 127 (7 << TIMING_CFG1_CASLAT_SHIFT) |\ 128 (4 << TIMING_CFG1_REFREC_SHIFT) |\ 129 (4 << TIMING_CFG1_WRREC_SHIFT) |\ 130 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ 131 (2 << TIMING_CFG1_WRTORD_SHIFT)) 132 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ 133 (5 << TIMING_CFG2_CPO_SHIFT) |\ 134 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ 135 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ 136 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ 137 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ 138 (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) 139 140 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ 141 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 142 143 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ 144 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ 145 SDRAM_CFG_DBW_32 |\ 146 SDRAM_CFG_SDRAM_TYPE_DDR2) 147 148 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 149 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ 150 (0x0242 << SDRAM_MODE_SD_SHIFT)) 151 #define CONFIG_SYS_DDR_MODE_2 0x00000000 152 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 153 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ 154 DDRCDR_PZ_NOMZ |\ 155 DDRCDR_NZ_NOMZ |\ 156 DDRCDR_ODT |\ 157 DDRCDR_M_ODR |\ 158 DDRCDR_Q_DRN) 159 160 /* 161 * on-board devices 162 */ 163 #define CONFIG_TSEC1 164 #define CONFIG_TSEC2 165 #define CONFIG_HARD_SPI 166 167 /* 168 * NOR FLASH setup 169 */ 170 #define CONFIG_SYS_FLASH_CFI 171 #define CONFIG_FLASH_CFI_DRIVER 172 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 173 #define CONFIG_FLASH_SHOW_PROGRESS 50 174 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 175 176 #define CONFIG_SYS_FLASH_BASE 0xFF800000 177 #define CONFIG_SYS_FLASH_SIZE 8 178 #define CONFIG_SYS_FLASH_PROTECTION 179 180 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 181 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 182 183 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 184 BR_PS_8 |\ 185 BR_MS_GPCM |\ 186 BR_V) 187 188 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 189 OR_GPCM_SCY_10 |\ 190 OR_GPCM_EHTR |\ 191 OR_GPCM_TRLX |\ 192 OR_GPCM_CSNT |\ 193 OR_GPCM_EAD) 194 #define CONFIG_SYS_MAX_FLASH_BANKS 1 195 #define CONFIG_SYS_MAX_FLASH_SECT 128 196 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 199 200 /* 201 * NAND FLASH setup 202 */ 203 #define CONFIG_SYS_NAND_BASE 0xE1000000 204 #define CONFIG_SYS_MAX_NAND_DEVICE 1 205 #define CONFIG_SYS_NAND_MAX_CHIPS 1 206 #define CONFIG_NAND_FSL_ELBC 207 #define CONFIG_SYS_NAND_PAGE_SIZE (2048) 208 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 209 #define NAND_CACHE_PAGES 64 210 211 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 212 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E 213 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 214 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 215 216 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ 217 (2<<BR_DECC_SHIFT) |\ 218 BR_PS_8 |\ 219 BR_MS_FCM |\ 220 BR_V) 221 222 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\ 223 OR_FCM_PGS |\ 224 OR_FCM_CSCT |\ 225 OR_FCM_CST |\ 226 OR_FCM_CHT |\ 227 OR_FCM_SCY_4 |\ 228 OR_FCM_TRLX |\ 229 OR_FCM_EHTR |\ 230 OR_FCM_RST) 231 232 /* 233 * MRAM setup 234 */ 235 #define CONFIG_SYS_MRAM_BASE 0xE2000000 236 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ 237 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE 238 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */ 239 240 #define CONFIG_SYS_OR_TIMING_MRAM 241 242 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ 243 BR_PS_8 |\ 244 BR_MS_GPCM |\ 245 BR_V) 246 247 #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74 248 249 /* 250 * CPLD setup 251 */ 252 #define CONFIG_SYS_CPLD_BASE 0xE3000000 253 #define CONFIG_SYS_CPLD_SIZE 0x8000 254 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE 255 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E 256 257 #define CONFIG_SYS_OR_TIMING_MRAM 258 259 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ 260 BR_PS_8 |\ 261 BR_MS_GPCM |\ 262 BR_V) 263 264 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814 265 266 /* 267 * HW-Watchdog 268 */ 269 #define CONFIG_WATCHDOG 1 270 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF 271 272 /* 273 * I2C setup 274 */ 275 #define CONFIG_SYS_I2C 276 #define CONFIG_SYS_I2C_FSL 277 #define CONFIG_SYS_FSL_I2C_SPEED 400000 278 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 279 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 280 #define CONFIG_RTC_PCF8563 281 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 282 283 /* 284 * SPI setup 285 */ 286 #ifdef CONFIG_HARD_SPI 287 #define CONFIG_SYS_GPIO1_PRELIM 288 #define CONFIG_SYS_GPIO1_DIR 0x00000001 289 #define CONFIG_SYS_GPIO1_DAT 0x00000001 290 #endif 291 292 /* 293 * Ethernet setup 294 */ 295 #ifdef CONFIG_TSEC1 296 #define CONFIG_HAS_ETH0 297 #define CONFIG_TSEC1_NAME "TSEC0" 298 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 299 #define TSEC1_PHY_ADDR 0x1 300 #define TSEC1_FLAGS TSEC_GIGABIT 301 #define TSEC1_PHYIDX 0 302 #endif 303 304 #ifdef CONFIG_TSEC2 305 #define CONFIG_HAS_ETH1 306 #define CONFIG_TSEC2_NAME "TSEC1" 307 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 308 #define TSEC2_PHY_ADDR 0x3 309 #define TSEC2_FLAGS TSEC_GIGABIT 310 #define TSEC2_PHYIDX 0 311 #endif 312 #define CONFIG_ETHPRIME "TSEC1" 313 314 /* 315 * Serial Port 316 */ 317 #define CONFIG_SYS_NS16550_SERIAL 318 #define CONFIG_SYS_NS16550_REG_SIZE 1 319 320 #define CONFIG_SYS_BAUDRATE_TABLE \ 321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 324 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) 325 326 #define CONFIG_HAS_FSL_DR_USB 327 #define CONFIG_SYS_SCCR_USBDRCM 3 328 329 /* 330 * BAT's 331 */ 332 #define CONFIG_HIGH_BATS 333 334 /* DDR @ 0x00000000 */ 335 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\ 336 BATL_PP_10) 337 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\ 338 BATU_BL_256M |\ 339 BATU_VS |\ 340 BATU_VP) 341 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 342 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 343 344 /* Initial RAM @ 0xFD000000 */ 345 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\ 346 BATL_PP_10 |\ 347 BATL_GUARDEDSTORAGE) 348 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\ 349 BATU_BL_256K |\ 350 BATU_VS |\ 351 BATU_VP) 352 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 353 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 354 355 /* FLASH @ 0xFF800000 */ 356 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\ 357 BATL_PP_10 |\ 358 BATL_GUARDEDSTORAGE) 359 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\ 360 BATU_BL_8M |\ 361 BATU_VS |\ 362 BATU_VP) 363 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\ 364 BATL_PP_10 |\ 365 BATL_CACHEINHIBIT |\ 366 BATL_GUARDEDSTORAGE) 367 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 368 369 #define CONFIG_SYS_IBAT3L (0) 370 #define CONFIG_SYS_IBAT3U (0) 371 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 372 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 373 374 #define CONFIG_SYS_IBAT4L (0) 375 #define CONFIG_SYS_IBAT4U (0) 376 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 377 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 378 379 /* IMMRBAR @ 0xF0000000 */ 380 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\ 381 BATL_PP_10 |\ 382 BATL_CACHEINHIBIT |\ 383 BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\ 385 BATU_BL_128M |\ 386 BATU_VS |\ 387 BATU_VP) 388 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 389 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 390 391 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */ 392 #define CONFIG_SYS_IBAT6L (0xE0000000 |\ 393 BATL_PP_10 |\ 394 BATL_GUARDEDSTORAGE) 395 #define CONFIG_SYS_IBAT6U (0xE0000000 |\ 396 BATU_BL_256M |\ 397 BATU_VS |\ 398 BATU_VP) 399 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 400 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 401 402 #define CONFIG_SYS_IBAT7L (0) 403 #define CONFIG_SYS_IBAT7U (0) 404 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 405 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 406 407 /* 408 * U-Boot environment setup 409 */ 410 #define CONFIG_BOOTP_BOOTFILESIZE 411 412 /* 413 * The reserved memory 414 */ 415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 416 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 417 #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) 418 419 /* 420 * Environment Configuration 421 */ 422 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ 423 + CONFIG_SYS_MONITOR_LEN) 424 #define CONFIG_ENV_SIZE 0x20000 425 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 426 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 427 428 #define CONFIG_NETDEV eth1 429 #define CONFIG_HOSTNAME "ids8313" 430 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" 431 #define CONFIG_BOOTFILE "ids8313/uImage" 432 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" 433 #define CONFIG_FDTFILE "ids8313/ids8313.dtb" 434 #define CONFIG_LOADADDR 0x400000 435 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" 436 437 /* Initial Memory map for Linux*/ 438 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 439 440 /* 441 * Miscellaneous configurable options 442 */ 443 #define CONFIG_SYS_CBSIZE 1024 444 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 445 446 #define CONFIG_SYS_MEMTEST_START 0x00001000 447 #define CONFIG_SYS_MEMTEST_END 0x00C00000 448 449 #define CONFIG_SYS_LOAD_ADDR 0x100000 450 #define CONFIG_MII 451 #define CONFIG_LOADS_ECHO 452 #define CONFIG_TIMESTAMP 453 #define CONFIG_PREBOOT "echo;" \ 454 "echo Type \\\"run nfsboot\\\" " \ 455 "to mount root filesystem over NFS;echo" 456 #define CONFIG_BOOTCOMMAND "run boot_cramfs" 457 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 458 459 #define CONFIG_JFFS2_NAND 460 #define CONFIG_JFFS2_DEV "0" 461 462 /* mtdparts command line support */ 463 #define CONFIG_FLASH_CFI_MTD 464 #define CONFIG_MTD_DEVICE 465 466 #define CONFIG_EXTRA_ENV_SETTINGS \ 467 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 468 "ethprime=TSEC1\0" \ 469 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 470 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ 471 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 472 " +${filesize}; " \ 473 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 474 " +${filesize}; " \ 475 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 476 " ${filesize}; " \ 477 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 478 " +${filesize}; " \ 479 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ 480 " ${filesize}\0" \ 481 "console=ttyS0\0" \ 482 "fdtaddr=0x780000\0" \ 483 "kernel_addr=ff800000\0" \ 484 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ 485 "setbootargs=setenv bootargs " \ 486 "root=${rootdev} rw console=${console}," \ 487 "${baudrate} ${othbootargs}\0" \ 488 "setipargs=setenv bootargs root=${rootdev} rw " \ 489 "nfsroot=${serverip}:${rootpath} " \ 490 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 491 "${netmask}:${hostname}:${netdev}:off " \ 492 "console=${console},${baudrate} ${othbootargs}\0" \ 493 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 494 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 495 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 496 "\0" 497 498 #define CONFIG_NFSBOOTCOMMAND \ 499 "setenv rootdev /dev/nfs;" \ 500 "run setipargs;run addmtd;" \ 501 "tftp ${loadaddr} ${bootfile};" \ 502 "tftp ${fdtaddr} ${fdtfile};" \ 503 "fdt addr ${fdtaddr};" \ 504 "bootm ${loadaddr} - ${fdtaddr}" 505 506 /* UBI Support */ 507 #define CONFIG_MTD_PARTITIONS 508 509 #define CONFIG_IMAGE_FORMAT_LEGACY 510 511 #endif /* __CONFIG_H */ 512