xref: /openbmc/u-boot/include/configs/ids8313.h (revision 3ebd892f)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2013
4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5  *
6  * Based on:
7  * Copyright (c) 2011 IDS GmbH, Germany
8  * Sergej Stepanov <ste@ids.de>
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_MPC831x
18 #define CONFIG_MPC8313
19 
20 #define CONFIG_FSL_ELBC
21 
22 #define CONFIG_MISC_INIT_R
23 
24 #define CONFIG_BOOT_RETRY_TIME		900
25 #define CONFIG_BOOT_RETRY_MIN		30
26 #define CONFIG_RESET_TO_RETRY
27 
28 #define CONFIG_83XX_CLKIN		66000000	/* in Hz */
29 #define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN
30 
31 #define CONFIG_SYS_IMMR		0xF0000000
32 
33 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
34 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
35 
36 /*
37  * Hardware Reset Configuration Word
38  * if CLKIN is 66.000MHz, then
39  * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
40  */
41 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
42 			     HRCWL_DDR_TO_SCB_CLK_2X1 |\
43 			     HRCWL_CSB_TO_CLKIN_2X1 |\
44 			     HRCWL_CORE_TO_CSB_2X1)
45 
46 #define CONFIG_SYS_HRCW_HIGH	(HRCWH_PCI_HOST |\
47 				 HRCWH_CORE_ENABLE |\
48 				 HRCWH_FROM_0XFFF00100 |\
49 				 HRCWH_BOOTSEQ_DISABLE |\
50 				 HRCWH_SW_WATCHDOG_DISABLE |\
51 				 HRCWH_ROM_LOC_LOCAL_8BIT |\
52 				 HRCWH_RL_EXT_LEGACY |\
53 				 HRCWH_TSEC1M_IN_MII |\
54 				 HRCWH_TSEC2M_IN_MII |\
55 				 HRCWH_BIG_ENDIAN)
56 
57 #define CONFIG_SYS_SICRH	0x00000000
58 #define CONFIG_SYS_SICRL	(SICRL_LBC | SICRL_SPI_D)
59 
60 #define CONFIG_HWCONFIG
61 
62 #define CONFIG_SYS_HID0_INIT	0x000000000
63 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK |\
64 				 HID0_ENABLE_INSTRUCTION_CACHE |\
65 				 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
66 
67 #define CONFIG_SYS_HID2	(HID2_HBE | 0x00020000)
68 
69 /*
70  * Definitions for initial stack pointer and data area (in DCACHE )
71  */
72 #define CONFIG_SYS_INIT_RAM_LOCK
73 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
74 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000  /* End of used area in DPRAM */
75 #define CONFIG_SYS_GBL_DATA_SIZE	0x100
76 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
77 					 - CONFIG_SYS_GBL_DATA_SIZE)
78 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
79 
80 /*
81  * Local Bus LCRR and LBCR regs
82  */
83 #define CONFIG_SYS_LCRR_EADC		LCRR_EADC_1
84 #define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
85 #define CONFIG_SYS_LBC_LBCR		(0x00040000 |\
86 					 (0xFF << LBCR_BMT_SHIFT) |\
87 					 0xF)
88 
89 #define CONFIG_SYS_LBC_MRTPR		0x20000000
90 
91 /*
92  * Internal Definitions
93  */
94 /*
95  * DDR Setup
96  */
97 #define CONFIG_SYS_DDR_BASE		0x00000000
98 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
99 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
100 
101 /*
102  * Manually set up DDR parameters,
103  * as this board has not the SPD connected to I2C.
104  */
105 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
106 #define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN |\
107 					 0x00010000 |\
108 					 CSCONFIG_ROW_BIT_13 |\
109 					 CSCONFIG_COL_BIT_10)
110 
111 #define CONFIG_SYS_DDR_CONFIG_256	(CONFIG_SYS_DDR_CONFIG | \
112 					 CSCONFIG_BANK_BIT_3)
113 
114 #define CONFIG_SYS_DDR_TIMING_3	(1 << 16)	/* ext refrec */
115 #define CONFIG_SYS_DDR_TIMING_0	((3 << TIMING_CFG0_RWT_SHIFT) |\
116 				(3 << TIMING_CFG0_WRT_SHIFT) |\
117 				(3 << TIMING_CFG0_RRT_SHIFT) |\
118 				(3 << TIMING_CFG0_WWT_SHIFT) |\
119 				(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
120 				(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
121 				(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
122 				(2 << TIMING_CFG0_MRS_CYC_SHIFT))
123 #define CONFIG_SYS_DDR_TIMING_1	((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
124 				(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
125 				(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
126 				(7 << TIMING_CFG1_CASLAT_SHIFT) |\
127 				(4 << TIMING_CFG1_REFREC_SHIFT) |\
128 				(4 << TIMING_CFG1_WRREC_SHIFT) |\
129 				(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
130 				(2 << TIMING_CFG1_WRTORD_SHIFT))
131 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
132 				(5 << TIMING_CFG2_CPO_SHIFT) |\
133 				(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
134 				(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
135 				(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
136 				(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
137 				(6 << TIMING_CFG2_FOUR_ACT_SHIFT))
138 
139 #define CONFIG_SYS_DDR_INTERVAL	((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
140 				(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
141 
142 #define CONFIG_SYS_SDRAM_CFG		(SDRAM_CFG_SREN |\
143 					 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
144 					 SDRAM_CFG_DBW_32 |\
145 					 SDRAM_CFG_SDRAM_TYPE_DDR2)
146 
147 #define CONFIG_SYS_SDRAM_CFG2		0x00401000
148 #define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
149 					 (0x0242 << SDRAM_MODE_SD_SHIFT))
150 #define CONFIG_SYS_DDR_MODE_2		0x00000000
151 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
152 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN |\
153 					 DDRCDR_PZ_NOMZ |\
154 					 DDRCDR_NZ_NOMZ |\
155 					 DDRCDR_ODT |\
156 					 DDRCDR_M_ODR |\
157 					 DDRCDR_Q_DRN)
158 
159 /*
160  * on-board devices
161  */
162 #define CONFIG_TSEC1
163 #define CONFIG_TSEC2
164 #define CONFIG_HARD_SPI
165 
166 /*
167  * NOR FLASH setup
168  */
169 #define CONFIG_SYS_FLASH_CFI
170 #define CONFIG_FLASH_CFI_DRIVER
171 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
172 #define CONFIG_FLASH_SHOW_PROGRESS	50
173 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
174 
175 #define CONFIG_SYS_FLASH_BASE		0xFF800000
176 #define CONFIG_SYS_FLASH_SIZE		8
177 #define CONFIG_SYS_FLASH_PROTECTION
178 
179 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
180 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016
181 
182 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |\
183 					 BR_PS_8 |\
184 					 BR_MS_GPCM |\
185 					 BR_V)
186 
187 #define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
188 					 OR_GPCM_SCY_10 |\
189 					 OR_GPCM_EHTR |\
190 					 OR_GPCM_TRLX |\
191 					 OR_GPCM_CSNT |\
192 					 OR_GPCM_EAD)
193 #define CONFIG_SYS_MAX_FLASH_BANKS	1
194 #define CONFIG_SYS_MAX_FLASH_SECT	128
195 
196 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000
197 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
198 
199 /*
200  * NAND FLASH setup
201  */
202 #define CONFIG_SYS_NAND_BASE		0xE1000000
203 #define CONFIG_SYS_MAX_NAND_DEVICE	1
204 #define CONFIG_SYS_NAND_MAX_CHIPS	1
205 #define CONFIG_NAND_FSL_ELBC
206 #define CONFIG_SYS_NAND_PAGE_SIZE	(2048)
207 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
208 #define NAND_CACHE_PAGES		64
209 
210 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
211 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E
212 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
213 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR1_PRELIM
214 
215 #define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_NAND_BASE) |\
216 				 (2<<BR_DECC_SHIFT) |\
217 				 BR_PS_8 |\
218 				 BR_MS_FCM |\
219 				 BR_V)
220 
221 #define CONFIG_SYS_OR1_PRELIM	(0xFFFF8000 |\
222 				 OR_FCM_PGS |\
223 				 OR_FCM_CSCT |\
224 				 OR_FCM_CST |\
225 				 OR_FCM_CHT |\
226 				 OR_FCM_SCY_4 |\
227 				 OR_FCM_TRLX |\
228 				 OR_FCM_EHTR |\
229 				 OR_FCM_RST)
230 
231 /*
232  * MRAM setup
233  */
234 #define CONFIG_SYS_MRAM_BASE		0xE2000000
235 #define CONFIG_SYS_MRAM_SIZE		0x20000	/* 128 Kb */
236 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_MRAM_BASE
237 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010	/* 128 Kb  */
238 
239 #define CONFIG_SYS_OR_TIMING_MRAM
240 
241 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_MRAM_BASE |\
242 					 BR_PS_8 |\
243 					 BR_MS_GPCM |\
244 					 BR_V)
245 
246 #define CONFIG_SYS_OR2_PRELIM		0xFFFE0C74
247 
248 /*
249  * CPLD setup
250  */
251 #define CONFIG_SYS_CPLD_BASE		0xE3000000
252 #define CONFIG_SYS_CPLD_SIZE		0x8000
253 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CPLD_BASE
254 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E
255 
256 #define CONFIG_SYS_OR_TIMING_MRAM
257 
258 #define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_CPLD_BASE |\
259 					 BR_PS_8 |\
260 					 BR_MS_GPCM |\
261 					 BR_V)
262 
263 #define CONFIG_SYS_OR3_PRELIM		0xFFFF8814
264 
265 /*
266  * HW-Watchdog
267  */
268 #define CONFIG_WATCHDOG		1
269 #define CONFIG_SYS_WATCHDOG_VALUE	0xFFFF
270 
271 /*
272  * I2C setup
273  */
274 #define CONFIG_SYS_I2C
275 #define CONFIG_SYS_I2C_FSL
276 #define CONFIG_SYS_FSL_I2C_SPEED	400000
277 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
278 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
279 #define CONFIG_RTC_PCF8563
280 #define CONFIG_SYS_I2C_RTC_ADDR	0x51
281 
282 /*
283  * SPI setup
284  */
285 #ifdef CONFIG_HARD_SPI
286 #define CONFIG_SYS_GPIO1_PRELIM
287 #define CONFIG_SYS_GPIO1_DIR		0x00000001
288 #define CONFIG_SYS_GPIO1_DAT		0x00000001
289 #endif
290 
291 /*
292  * Ethernet setup
293  */
294 #ifdef CONFIG_TSEC1
295 #define CONFIG_HAS_ETH0
296 #define CONFIG_TSEC1_NAME		"TSEC0"
297 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
298 #define TSEC1_PHY_ADDR			0x1
299 #define TSEC1_FLAGS			TSEC_GIGABIT
300 #define TSEC1_PHYIDX			0
301 #endif
302 
303 #ifdef CONFIG_TSEC2
304 #define CONFIG_HAS_ETH1
305 #define CONFIG_TSEC2_NAME		"TSEC1"
306 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
307 #define TSEC2_PHY_ADDR			0x3
308 #define TSEC2_FLAGS			TSEC_GIGABIT
309 #define TSEC2_PHYIDX			0
310 #endif
311 #define CONFIG_ETHPRIME		"TSEC1"
312 
313 /*
314  * Serial Port
315  */
316 #define CONFIG_SYS_NS16550_SERIAL
317 #define CONFIG_SYS_NS16550_REG_SIZE	1
318 
319 #define CONFIG_SYS_BAUDRATE_TABLE	\
320 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
321 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
322 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
323 #define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
324 
325 #define CONFIG_HAS_FSL_DR_USB
326 #define CONFIG_SYS_SCCR_USBDRCM	3
327 
328 /*
329  * BAT's
330  */
331 #define CONFIG_HIGH_BATS
332 
333 /* DDR @ 0x00000000 */
334 #define CONFIG_SYS_IBAT0L		(CONFIG_SYS_SDRAM_BASE |\
335 					 BATL_PP_10)
336 #define CONFIG_SYS_IBAT0U		(CONFIG_SYS_SDRAM_BASE |\
337 					 BATU_BL_256M |\
338 					 BATU_VS |\
339 					 BATU_VP)
340 #define CONFIG_SYS_DBAT0L		CONFIG_SYS_IBAT0L
341 #define CONFIG_SYS_DBAT0U		CONFIG_SYS_IBAT0U
342 
343 /* Initial RAM @ 0xFD000000 */
344 #define CONFIG_SYS_IBAT1L		(CONFIG_SYS_INIT_RAM_ADDR |\
345 					 BATL_PP_10 |\
346 					 BATL_GUARDEDSTORAGE)
347 #define CONFIG_SYS_IBAT1U		(CONFIG_SYS_INIT_RAM_ADDR |\
348 					 BATU_BL_256K |\
349 					 BATU_VS |\
350 					 BATU_VP)
351 #define CONFIG_SYS_DBAT1L		CONFIG_SYS_IBAT1L
352 #define CONFIG_SYS_DBAT1U		CONFIG_SYS_IBAT1U
353 
354 /* FLASH @ 0xFF800000 */
355 #define CONFIG_SYS_IBAT2L		(CONFIG_SYS_FLASH_BASE |\
356 					 BATL_PP_10 |\
357 					 BATL_GUARDEDSTORAGE)
358 #define CONFIG_SYS_IBAT2U		(CONFIG_SYS_FLASH_BASE |\
359 					 BATU_BL_8M |\
360 					 BATU_VS |\
361 					 BATU_VP)
362 #define CONFIG_SYS_DBAT2L		(CONFIG_SYS_FLASH_BASE |\
363 					 BATL_PP_10 |\
364 					 BATL_CACHEINHIBIT |\
365 					 BATL_GUARDEDSTORAGE)
366 #define CONFIG_SYS_DBAT2U		CONFIG_SYS_IBAT2U
367 
368 #define CONFIG_SYS_IBAT3L		(0)
369 #define CONFIG_SYS_IBAT3U		(0)
370 #define CONFIG_SYS_DBAT3L		CONFIG_SYS_IBAT3L
371 #define CONFIG_SYS_DBAT3U		CONFIG_SYS_IBAT3U
372 
373 #define CONFIG_SYS_IBAT4L		(0)
374 #define CONFIG_SYS_IBAT4U		(0)
375 #define CONFIG_SYS_DBAT4L		CONFIG_SYS_IBAT4L
376 #define CONFIG_SYS_DBAT4U		CONFIG_SYS_IBAT4U
377 
378 /* IMMRBAR @ 0xF0000000 */
379 #define CONFIG_SYS_IBAT5L		(CONFIG_SYS_IMMR |\
380 					 BATL_PP_10 |\
381 					 BATL_CACHEINHIBIT |\
382 					 BATL_GUARDEDSTORAGE)
383 #define CONFIG_SYS_IBAT5U		(CONFIG_SYS_IMMR |\
384 					 BATU_BL_128M |\
385 					 BATU_VS |\
386 					 BATU_VP)
387 #define CONFIG_SYS_DBAT5L		CONFIG_SYS_IBAT5L
388 #define CONFIG_SYS_DBAT5U		CONFIG_SYS_IBAT5U
389 
390 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
391 #define CONFIG_SYS_IBAT6L		(0xE0000000 |\
392 					 BATL_PP_10 |\
393 					 BATL_GUARDEDSTORAGE)
394 #define CONFIG_SYS_IBAT6U		(0xE0000000 |\
395 					 BATU_BL_256M |\
396 					 BATU_VS |\
397 					 BATU_VP)
398 #define CONFIG_SYS_DBAT6L		CONFIG_SYS_IBAT6L
399 #define CONFIG_SYS_DBAT6U		CONFIG_SYS_IBAT6U
400 
401 #define CONFIG_SYS_IBAT7L		(0)
402 #define CONFIG_SYS_IBAT7U		(0)
403 #define CONFIG_SYS_DBAT7L		CONFIG_SYS_IBAT7L
404 #define CONFIG_SYS_DBAT7U		CONFIG_SYS_IBAT7U
405 
406 /*
407  * U-Boot environment setup
408  */
409 #define CONFIG_BOOTP_BOOTFILESIZE
410 
411 /*
412  * The reserved memory
413  */
414 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
415 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
416 #define CONFIG_SYS_MALLOC_LEN		(8 * 1024 * 1024)
417 
418 /*
419  * Environment Configuration
420  */
421 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
422 				+ CONFIG_SYS_MONITOR_LEN)
423 #define CONFIG_ENV_SIZE		0x20000
424 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
425 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
426 
427 #define CONFIG_NETDEV			eth1
428 #define CONFIG_HOSTNAME		"ids8313"
429 #define CONFIG_ROOTPATH		"/opt/eldk-4.2/ppc_6xx"
430 #define CONFIG_BOOTFILE		"ids8313/uImage"
431 #define CONFIG_UBOOTPATH		"ids8313/u-boot.bin"
432 #define CONFIG_FDTFILE			"ids8313/ids8313.dtb"
433 #define CONFIG_LOADADDR		0x400000
434 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
435 
436 /* Initial Memory map for Linux*/
437 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
438 
439 /*
440  * Miscellaneous configurable options
441  */
442 #define CONFIG_SYS_CBSIZE		1024
443 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
444 
445 #define CONFIG_SYS_MEMTEST_START	0x00001000
446 #define CONFIG_SYS_MEMTEST_END		0x00C00000
447 
448 #define CONFIG_SYS_LOAD_ADDR		0x100000
449 #define CONFIG_MII
450 #define CONFIG_LOADS_ECHO
451 #define CONFIG_TIMESTAMP
452 #define CONFIG_PREBOOT			"echo;" \
453 					"echo Type \\\"run nfsboot\\\" " \
454 					"to mount root filesystem over NFS;echo"
455 #define CONFIG_BOOTCOMMAND		"run boot_cramfs"
456 #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
457 
458 #define CONFIG_JFFS2_NAND
459 #define CONFIG_JFFS2_DEV		"0"
460 
461 /* mtdparts command line support */
462 #define CONFIG_FLASH_CFI_MTD
463 #define CONFIG_MTD_DEVICE
464 
465 #define CONFIG_EXTRA_ENV_SETTINGS \
466 	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
467 	"ethprime=TSEC1\0"						\
468 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
469 	"tftpflash=tftpboot ${loadaddr} ${uboot}; "			\
470 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
471 		" +${filesize}; "					\
472 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
473 		" +${filesize}; "					\
474 		"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
475 		" ${filesize}; "					\
476 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
477 		" +${filesize}; "					\
478 		"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
479 		" ${filesize}\0"					\
480 	"console=ttyS0\0"						\
481 	"fdtaddr=0x780000\0"						\
482 	"kernel_addr=ff800000\0"					\
483 	"fdtfile=" __stringify(CONFIG_FDTFILE) "\0"			\
484 	"setbootargs=setenv bootargs "					\
485 		"root=${rootdev} rw console=${console},"		\
486 			"${baudrate} ${othbootargs}\0"			\
487 	"setipargs=setenv bootargs root=${rootdev} rw "			\
488 			"nfsroot=${serverip}:${rootpath} "		\
489 			"ip=${ipaddr}:${serverip}:${gatewayip}:"	\
490 			"${netmask}:${hostname}:${netdev}:off "		\
491 			"console=${console},${baudrate} ${othbootargs}\0" \
492 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
493 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
494 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
495 	"\0"
496 
497 #define CONFIG_NFSBOOTCOMMAND						\
498 	"setenv rootdev /dev/nfs;"					\
499 	"run setipargs;run addmtd;"					\
500 	"tftp ${loadaddr} ${bootfile};"				\
501 	"tftp ${fdtaddr} ${fdtfile};"					\
502 	"fdt addr ${fdtaddr};"						\
503 	"bootm ${loadaddr} - ${fdtaddr}"
504 
505 /* UBI Support */
506 #define CONFIG_MTD_PARTITIONS
507 
508 #endif	/* __CONFIG_H */
509