1 /* 2 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_HSDK_H_ 8 #define _CONFIG_HSDK_H_ 9 10 #include <linux/sizes.h> 11 12 /* 13 * CPU configuration 14 */ 15 #define ARC_PERIPHERAL_BASE 0xF0000000 16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) 17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) 18 19 /* 20 * Memory configuration 21 */ 22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 23 24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 26 #define CONFIG_SYS_SDRAM_SIZE SZ_1G 27 28 #define CONFIG_SYS_INIT_SP_ADDR \ 29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 30 31 #define CONFIG_SYS_MALLOC_LEN SZ_2M 32 #define CONFIG_SYS_BOOTM_LEN SZ_32M 33 #define CONFIG_SYS_LOAD_ADDR 0x82000000 34 35 /* 36 * This board might be of different versions so handle it 37 */ 38 #define CONFIG_BOARD_TYPES 39 40 /* 41 * UART configuration 42 */ 43 #define CONFIG_DW_SERIAL 44 #define CONFIG_SYS_NS16550_SERIAL 45 #define CONFIG_SYS_NS16550_CLK 33330000 46 #define CONFIG_SYS_NS16550_MEM32 47 48 /* 49 * Ethernet PHY configuration 50 */ 51 #define CONFIG_MII 52 53 /* 54 * USB 1.1 configuration 55 */ 56 #define CONFIG_USB_OHCI_NEW 57 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 58 59 /* 60 * Environment settings 61 */ 62 #define CONFIG_ENV_SIZE SZ_16K 63 64 /* 65 * Environment configuration 66 */ 67 #define CONFIG_BOOTFILE "uImage" 68 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 69 70 /* 71 * Console configuration 72 */ 73 #define CONFIG_AUTO_COMPLETE 74 #define CONFIG_CMDLINE_EDITING 75 #define CONFIG_SYS_LONGHELP 76 77 /* 78 * Misc utility configuration 79 */ 80 #define CONFIG_BOUNCE_BUFFER 81 82 #endif /* _CONFIG_HSDK_H_ */ 83