1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef _CONFIG_HSDK_H_ 7 #define _CONFIG_HSDK_H_ 8 9 #include <linux/sizes.h> 10 11 /* 12 * CPU configuration 13 */ 14 #define NR_CPUS 4 15 #define ARC_PERIPHERAL_BASE 0xF0000000 16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) 17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) 18 19 /* 20 * Memory configuration 21 */ 22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 23 24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 26 #define CONFIG_SYS_SDRAM_SIZE SZ_1G 27 28 #define CONFIG_SYS_INIT_SP_ADDR \ 29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 30 31 #define CONFIG_SYS_MALLOC_LEN SZ_2M 32 #define CONFIG_SYS_BOOTM_LEN SZ_128M 33 #define CONFIG_SYS_LOAD_ADDR 0x82000000 34 35 /* 36 * UART configuration 37 */ 38 #define CONFIG_SYS_NS16550_SERIAL 39 #define CONFIG_SYS_NS16550_CLK 33330000 40 #define CONFIG_SYS_NS16550_MEM32 41 42 /* 43 * Ethernet PHY configuration 44 */ 45 46 /* 47 * USB 1.1 configuration 48 */ 49 #define CONFIG_USB_OHCI_NEW 50 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 51 52 /* 53 * Environment settings 54 */ 55 #define CONFIG_EXTRA_ENV_SETTINGS \ 56 "upgrade=if mmc rescan && " \ 57 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ 58 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ 59 "\"Fail to upgrade.\n" \ 60 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ 61 "; fi\0" \ 62 "core_dccm_0=0x10\0" \ 63 "core_dccm_1=0x6\0" \ 64 "core_dccm_2=0x10\0" \ 65 "core_dccm_3=0x6\0" \ 66 "core_iccm_0=0x10\0" \ 67 "core_iccm_1=0x6\0" \ 68 "core_iccm_2=0x10\0" \ 69 "core_iccm_3=0x6\0" \ 70 "core_mask=0xF\0" \ 71 "dcache_ena=0x1\0" \ 72 "icache_ena=0x1\0" \ 73 "non_volatile_limit=0xE\0" \ 74 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \ 75 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ 76 setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \ 77 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \ 78 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 79 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ 80 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ 81 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 82 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ 83 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \ 84 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 85 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ 86 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ 87 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ 88 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ 89 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \ 90 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 91 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ 92 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ 93 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \ 94 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 95 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ 96 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 97 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ 98 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \ 99 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ 100 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ 101 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ 102 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ 103 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" 104 105 /* 106 * Environment configuration 107 */ 108 #define CONFIG_BOOTFILE "uImage" 109 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 110 111 /* Cli configuration */ 112 #define CONFIG_SYS_CBSIZE SZ_2K 113 114 /* 115 * Callback configuration 116 */ 117 #define CONFIG_BOARD_LATE_INIT 118 119 #endif /* _CONFIG_HSDK_H_ */ 120