1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_R 24 #define CONFIG_LAST_STAGE_INIT 25 26 #define CONFIG_FSL_ESDHC 27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 28 29 #define CONFIG_CMD_IOLOOP 30 31 /* 32 * System Clock Setup 33 */ 34 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 35 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 36 37 /* 38 * Hardware Reset Configuration Word 39 * if CLKIN is 66.66MHz, then 40 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 41 * We choose the A type silicon as default, so the core is 400Mhz. 42 */ 43 #define CONFIG_SYS_HRCW_LOW (\ 44 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 45 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 46 HRCWL_SVCOD_DIV_2 |\ 47 HRCWL_CSB_TO_CLKIN_4X1 |\ 48 HRCWL_CORE_TO_CSB_3X1) 49 /* 50 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 51 * in 8308's HRCWH according to the manual, but original Freescale's 52 * code has them and I've expirienced some problems using the board 53 * with BDI3000 attached when I've tried to set these bits to zero 54 * (UART doesn't work after the 'reset run' command). 55 */ 56 #define CONFIG_SYS_HRCW_HIGH (\ 57 HRCWH_PCI_HOST |\ 58 HRCWH_PCI1_ARBITER_ENABLE |\ 59 HRCWH_CORE_ENABLE |\ 60 HRCWH_FROM_0XFFF00100 |\ 61 HRCWH_BOOTSEQ_DISABLE |\ 62 HRCWH_SW_WATCHDOG_DISABLE |\ 63 HRCWH_ROM_LOC_LOCAL_16BIT |\ 64 HRCWH_RL_EXT_LEGACY |\ 65 HRCWH_TSEC1M_IN_RGMII |\ 66 HRCWH_TSEC2M_IN_RGMII |\ 67 HRCWH_BIG_ENDIAN) 68 69 /* 70 * System IO Config 71 */ 72 #define CONFIG_SYS_SICRH (\ 73 SICRH_ESDHC_A_SD |\ 74 SICRH_ESDHC_B_SD |\ 75 SICRH_ESDHC_C_SD |\ 76 SICRH_GPIO_A_GPIO |\ 77 SICRH_GPIO_B_GPIO |\ 78 SICRH_IEEE1588_A_GPIO |\ 79 SICRH_USB |\ 80 SICRH_GTM_GPIO |\ 81 SICRH_IEEE1588_B_GPIO |\ 82 SICRH_ETSEC2_GPIO |\ 83 SICRH_GPIOSEL_1 |\ 84 SICRH_TMROBI_V3P3 |\ 85 SICRH_TSOBI1_V2P5 |\ 86 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 87 #define CONFIG_SYS_SICRL (\ 88 SICRL_SPI_PF0 |\ 89 SICRL_UART_PF0 |\ 90 SICRL_IRQ_PF0 |\ 91 SICRL_I2C2_PF0 |\ 92 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 93 94 /* 95 * IMMR new address 96 */ 97 #define CONFIG_SYS_IMMR 0xE0000000 98 99 /* 100 * SERDES 101 */ 102 #define CONFIG_FSL_SERDES 103 #define CONFIG_FSL_SERDES1 0xe3000 104 105 /* 106 * Arbiter Setup 107 */ 108 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 109 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 110 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 111 112 /* 113 * DDR Setup 114 */ 115 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 119 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 120 | DDRCDR_PZ_LOZ \ 121 | DDRCDR_NZ_LOZ \ 122 | DDRCDR_ODT \ 123 | DDRCDR_Q_DRN) 124 /* 0x7b880001 */ 125 /* 126 * Manually set up DDR parameters 127 * consist of one chip NT5TU64M16HG from NANYA 128 */ 129 130 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 131 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 133 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 134 | CSCONFIG_ODT_RD_NEVER \ 135 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 136 | CSCONFIG_BANK_BIT_3 \ 137 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 138 /* 0x80010102 */ 139 #define CONFIG_SYS_DDR_TIMING_3 0 140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 141 | (0 << TIMING_CFG0_WRT_SHIFT) \ 142 | (0 << TIMING_CFG0_RRT_SHIFT) \ 143 | (0 << TIMING_CFG0_WWT_SHIFT) \ 144 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 145 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 146 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 147 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 148 /* 0x00260802 */ 149 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 150 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 151 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 152 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 153 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 154 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 156 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 157 /* 0x26279222 */ 158 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 159 | (4 << TIMING_CFG2_CPO_SHIFT) \ 160 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 161 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 162 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 163 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 164 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 165 /* 0x021848c5 */ 166 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 167 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 168 /* 0x08240100 */ 169 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 170 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 171 | SDRAM_CFG_DBW_16) 172 /* 0x43100000 */ 173 174 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 175 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 176 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 177 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 178 #define CONFIG_SYS_DDR_MODE2 0x00000000 179 180 /* 181 * Memory test 182 */ 183 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 184 #define CONFIG_SYS_MEMTEST_END 0x07f00000 185 186 /* 187 * The reserved memory 188 */ 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 190 191 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 192 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 193 194 /* 195 * Initial RAM Base Address Setup 196 */ 197 #define CONFIG_SYS_INIT_RAM_LOCK 1 198 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 199 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 200 #define CONFIG_SYS_GBL_DATA_OFFSET \ 201 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 202 203 /* 204 * Local Bus Configuration & Clock Setup 205 */ 206 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 207 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 208 #define CONFIG_SYS_LBC_LBCR 0x00040000 209 210 /* 211 * FLASH on the Local Bus 212 */ 213 #if 1 214 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 215 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 216 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 217 #define CONFIG_FLASH_CFI_LEGACY 218 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 219 #endif 220 221 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 222 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 223 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 224 225 /* Window base at flash base */ 226 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 227 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 228 229 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 230 | BR_PS_16 /* 16 bit port */ \ 231 | BR_MS_GPCM /* MSEL = GPCM */ \ 232 | BR_V) /* valid */ 233 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 234 | OR_UPM_XAM \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_ACS_DIV2 \ 237 | OR_GPCM_XACS \ 238 | OR_GPCM_SCY_15 \ 239 | OR_GPCM_TRLX_SET \ 240 | OR_GPCM_EHTR_SET) 241 242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 243 #define CONFIG_SYS_MAX_FLASH_SECT 135 244 245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 247 248 /* 249 * FPGA 250 */ 251 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 252 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 253 254 /* Window base at FPGA base */ 255 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 256 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 257 258 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 259 | BR_PS_16 /* 16 bit port */ \ 260 | BR_MS_GPCM /* MSEL = GPCM */ \ 261 | BR_V) /* valid */ 262 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 263 | OR_UPM_XAM \ 264 | OR_GPCM_CSNT \ 265 | OR_GPCM_ACS_DIV2 \ 266 | OR_GPCM_XACS \ 267 | OR_GPCM_SCY_15 \ 268 | OR_GPCM_TRLX_SET \ 269 | OR_GPCM_EHTR_SET) 270 271 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 272 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 273 274 #define CONFIG_SYS_FPGA_COUNT 1 275 276 #define CONFIG_SYS_MCLINK_MAX 3 277 278 #define CONFIG_SYS_FPGA_PTR \ 279 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 280 281 /* 282 * Serial Port 283 */ 284 #define CONFIG_CONS_INDEX 2 285 #define CONFIG_SYS_NS16550_SERIAL 286 #define CONFIG_SYS_NS16550_REG_SIZE 1 287 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 288 289 #define CONFIG_SYS_BAUDRATE_TABLE \ 290 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 291 292 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 293 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 294 295 /* Pass open firmware flat tree */ 296 297 /* I2C */ 298 #define CONFIG_SYS_I2C 299 #define CONFIG_SYS_I2C_FSL 300 #define CONFIG_SYS_FSL_I2C_SPEED 400000 301 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 302 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 303 304 #define CONFIG_PCA953X /* NXP PCA9554 */ 305 #define CONFIG_PCA9698 /* NXP PCA9698 */ 306 307 #define CONFIG_SYS_I2C_IHS 308 #define CONFIG_SYS_I2C_IHS_CH0 309 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 310 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 311 #define CONFIG_SYS_I2C_IHS_CH1 312 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 313 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 314 #define CONFIG_SYS_I2C_IHS_CH2 315 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 316 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 317 #define CONFIG_SYS_I2C_IHS_CH3 318 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 319 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 320 321 #ifdef CONFIG_HRCON_DH 322 #define CONFIG_SYS_I2C_IHS_DUAL 323 #define CONFIG_SYS_I2C_IHS_CH0_1 324 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 325 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 326 #define CONFIG_SYS_I2C_IHS_CH1_1 327 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 328 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 329 #define CONFIG_SYS_I2C_IHS_CH2_1 330 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 331 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 332 #define CONFIG_SYS_I2C_IHS_CH3_1 333 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 334 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 335 #endif 336 337 /* 338 * Software (bit-bang) I2C driver configuration 339 */ 340 #define CONFIG_SYS_I2C_SOFT 341 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 342 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 343 #define I2C_SOFT_DECLARATIONS2 344 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 345 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 346 #define I2C_SOFT_DECLARATIONS3 347 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 348 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 349 #define I2C_SOFT_DECLARATIONS4 350 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 351 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 352 #define I2C_SOFT_DECLARATIONS5 353 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 354 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 355 #define I2C_SOFT_DECLARATIONS6 356 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 357 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 358 #define I2C_SOFT_DECLARATIONS7 359 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 360 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 361 #define I2C_SOFT_DECLARATIONS8 362 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 364 365 #ifdef CONFIG_HRCON_DH 366 #define I2C_SOFT_DECLARATIONS9 367 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 368 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 369 #define I2C_SOFT_DECLARATIONS10 370 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 371 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 372 #define I2C_SOFT_DECLARATIONS11 373 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 374 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 375 #define I2C_SOFT_DECLARATIONS12 376 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 378 #endif 379 380 #ifdef CONFIG_HRCON_DH 381 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 382 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 383 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 384 {12, 0x4c} } 385 #else 386 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 387 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 388 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 389 {8, 0x4c} } 390 #endif 391 392 #ifndef __ASSEMBLY__ 393 void fpga_gpio_set(unsigned int bus, int pin); 394 void fpga_gpio_clear(unsigned int bus, int pin); 395 int fpga_gpio_get(unsigned int bus, int pin); 396 void fpga_control_set(unsigned int bus, int pin); 397 void fpga_control_clear(unsigned int bus, int pin); 398 #endif 399 400 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 401 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 402 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 403 404 #ifdef CONFIG_HRCON_DH 405 #define I2C_ACTIVE \ 406 do { \ 407 if (I2C_ADAP_HWNR > 7) \ 408 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 409 else \ 410 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 411 } while (0) 412 #else 413 #define I2C_ACTIVE { } 414 #endif 415 #define I2C_TRISTATE { } 416 #define I2C_READ \ 417 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 418 #define I2C_SDA(bit) \ 419 do { \ 420 if (bit) \ 421 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 422 else \ 423 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 424 } while (0) 425 #define I2C_SCL(bit) \ 426 do { \ 427 if (bit) \ 428 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 429 else \ 430 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 431 } while (0) 432 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 433 434 /* 435 * Software (bit-bang) MII driver configuration 436 */ 437 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 438 #define CONFIG_BITBANGMII_MULTI 439 440 /* 441 * OSD Setup 442 */ 443 #define CONFIG_SYS_OSD_SCREENS 1 444 #define CONFIG_SYS_DP501_DIFFERENTIAL 445 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 446 447 #ifdef CONFIG_HRCON_DH 448 #define CONFIG_SYS_OSD_DH 449 #endif 450 451 /* 452 * General PCI 453 * Addresses are mapped 1-1. 454 */ 455 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 456 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 457 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 458 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 459 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 460 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 461 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 462 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 463 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 464 465 /* enable PCIE clock */ 466 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 467 468 #define CONFIG_PCI_INDIRECT_BRIDGE 469 #define CONFIG_PCIE 470 471 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 472 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 473 474 /* 475 * TSEC 476 */ 477 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 478 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 479 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 480 481 /* 482 * TSEC ethernet configuration 483 */ 484 #define CONFIG_MII 1 /* MII PHY management */ 485 #define CONFIG_TSEC1 486 #define CONFIG_TSEC1_NAME "eTSEC0" 487 #define TSEC1_PHY_ADDR 1 488 #define TSEC1_PHYIDX 0 489 #define TSEC1_FLAGS TSEC_GIGABIT 490 491 /* Options are: eTSEC[0-1] */ 492 #define CONFIG_ETHPRIME "eTSEC0" 493 494 /* 495 * Environment 496 */ 497 #if 1 498 #define CONFIG_ENV_IS_IN_FLASH 1 499 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 500 CONFIG_SYS_MONITOR_LEN) 501 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 502 #define CONFIG_ENV_SIZE 0x2000 503 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 504 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 505 #else 506 #define CONFIG_ENV_IS_NOWHERE 507 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 508 #endif 509 510 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 511 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 512 513 /* 514 * Command line configuration. 515 */ 516 #define CONFIG_CMD_PCI 517 518 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 519 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 520 521 /* 522 * Miscellaneous configurable options 523 */ 524 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 525 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 526 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 527 528 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 529 530 /* Print Buffer Size */ 531 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 532 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 533 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 534 535 /* 536 * For booting Linux, the board info and command line data 537 * have to be in the first 256 MB of memory, since this is 538 * the maximum mapped by the Linux kernel during initialization. 539 */ 540 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 541 542 /* 543 * Core HID Setup 544 */ 545 #define CONFIG_SYS_HID0_INIT 0x000000000 546 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 547 HID0_ENABLE_INSTRUCTION_CACHE | \ 548 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 549 #define CONFIG_SYS_HID2 HID2_HBE 550 551 /* 552 * MMU Setup 553 */ 554 555 /* DDR: cache cacheable */ 556 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 557 BATL_MEMCOHERENCE) 558 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 559 BATU_VS | BATU_VP) 560 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 561 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 562 563 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 564 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 565 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 566 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 567 BATU_VP) 568 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 569 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 570 571 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 572 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 573 BATL_MEMCOHERENCE) 574 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 575 BATU_VS | BATU_VP) 576 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 577 BATL_CACHEINHIBIT | \ 578 BATL_GUARDEDSTORAGE) 579 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 580 581 /* Stack in dcache: cacheable, no memory coherence */ 582 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 583 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 584 BATU_VS | BATU_VP) 585 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 586 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 587 588 /* 589 * Environment Configuration 590 */ 591 592 #define CONFIG_ENV_OVERWRITE 593 594 #if defined(CONFIG_TSEC_ENET) 595 #define CONFIG_HAS_ETH0 596 #endif 597 598 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 599 600 601 #define CONFIG_HOSTNAME hrcon 602 #define CONFIG_ROOTPATH "/opt/nfsroot" 603 #define CONFIG_BOOTFILE "uImage" 604 605 #define CONFIG_PREBOOT /* enable preboot variable */ 606 607 #define CONFIG_EXTRA_ENV_SETTINGS \ 608 "netdev=eth0\0" \ 609 "consoledev=ttyS1\0" \ 610 "u-boot=u-boot.bin\0" \ 611 "kernel_addr=1000000\0" \ 612 "fdt_addr=C00000\0" \ 613 "fdtfile=hrcon.dtb\0" \ 614 "load=tftp ${loadaddr} ${u-boot}\0" \ 615 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 616 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 617 " +${filesize};cp.b ${fileaddr} " \ 618 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 619 "upd=run load update\0" \ 620 621 #define CONFIG_NFSBOOTCOMMAND \ 622 "setenv bootargs root=/dev/nfs rw " \ 623 "nfsroot=$serverip:$rootpath " \ 624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 625 "console=$consoledev,$baudrate $othbootargs;" \ 626 "tftp ${kernel_addr} $bootfile;" \ 627 "tftp ${fdt_addr} $fdtfile;" \ 628 "bootm ${kernel_addr} - ${fdt_addr}" 629 630 #define CONFIG_MMCBOOTCOMMAND \ 631 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 634 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 635 "bootm ${kernel_addr} - ${fdt_addr}" 636 637 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 638 639 #endif /* __CONFIG_H */ 640