1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_R 24 #define CONFIG_LAST_STAGE_INIT 25 26 #define CONFIG_FSL_ESDHC 27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 28 29 #define CONFIG_CMD_FPGAD 30 #define CONFIG_CMD_IOLOOP 31 32 /* 33 * System Clock Setup 34 */ 35 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 36 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 37 38 /* 39 * Hardware Reset Configuration Word 40 * if CLKIN is 66.66MHz, then 41 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 42 * We choose the A type silicon as default, so the core is 400Mhz. 43 */ 44 #define CONFIG_SYS_HRCW_LOW (\ 45 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 46 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 47 HRCWL_SVCOD_DIV_2 |\ 48 HRCWL_CSB_TO_CLKIN_4X1 |\ 49 HRCWL_CORE_TO_CSB_3X1) 50 /* 51 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 52 * in 8308's HRCWH according to the manual, but original Freescale's 53 * code has them and I've expirienced some problems using the board 54 * with BDI3000 attached when I've tried to set these bits to zero 55 * (UART doesn't work after the 'reset run' command). 56 */ 57 #define CONFIG_SYS_HRCW_HIGH (\ 58 HRCWH_PCI_HOST |\ 59 HRCWH_PCI1_ARBITER_ENABLE |\ 60 HRCWH_CORE_ENABLE |\ 61 HRCWH_FROM_0XFFF00100 |\ 62 HRCWH_BOOTSEQ_DISABLE |\ 63 HRCWH_SW_WATCHDOG_DISABLE |\ 64 HRCWH_ROM_LOC_LOCAL_16BIT |\ 65 HRCWH_RL_EXT_LEGACY |\ 66 HRCWH_TSEC1M_IN_RGMII |\ 67 HRCWH_TSEC2M_IN_RGMII |\ 68 HRCWH_BIG_ENDIAN) 69 70 /* 71 * System IO Config 72 */ 73 #define CONFIG_SYS_SICRH (\ 74 SICRH_ESDHC_A_SD |\ 75 SICRH_ESDHC_B_SD |\ 76 SICRH_ESDHC_C_SD |\ 77 SICRH_GPIO_A_GPIO |\ 78 SICRH_GPIO_B_GPIO |\ 79 SICRH_IEEE1588_A_GPIO |\ 80 SICRH_USB |\ 81 SICRH_GTM_GPIO |\ 82 SICRH_IEEE1588_B_GPIO |\ 83 SICRH_ETSEC2_GPIO |\ 84 SICRH_GPIOSEL_1 |\ 85 SICRH_TMROBI_V3P3 |\ 86 SICRH_TSOBI1_V2P5 |\ 87 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 88 #define CONFIG_SYS_SICRL (\ 89 SICRL_SPI_PF0 |\ 90 SICRL_UART_PF0 |\ 91 SICRL_IRQ_PF0 |\ 92 SICRL_I2C2_PF0 |\ 93 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 94 95 /* 96 * IMMR new address 97 */ 98 #define CONFIG_SYS_IMMR 0xE0000000 99 100 /* 101 * SERDES 102 */ 103 #define CONFIG_FSL_SERDES 104 #define CONFIG_FSL_SERDES1 0xe3000 105 106 /* 107 * Arbiter Setup 108 */ 109 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 110 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 111 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 112 113 /* 114 * DDR Setup 115 */ 116 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 119 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 120 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 121 | DDRCDR_PZ_LOZ \ 122 | DDRCDR_NZ_LOZ \ 123 | DDRCDR_ODT \ 124 | DDRCDR_Q_DRN) 125 /* 0x7b880001 */ 126 /* 127 * Manually set up DDR parameters 128 * consist of one chip NT5TU64M16HG from NANYA 129 */ 130 131 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 132 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 134 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 135 | CSCONFIG_ODT_RD_NEVER \ 136 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 137 | CSCONFIG_BANK_BIT_3 \ 138 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 139 /* 0x80010102 */ 140 #define CONFIG_SYS_DDR_TIMING_3 0 141 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 142 | (0 << TIMING_CFG0_WRT_SHIFT) \ 143 | (0 << TIMING_CFG0_RRT_SHIFT) \ 144 | (0 << TIMING_CFG0_WWT_SHIFT) \ 145 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 146 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 147 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 148 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 149 /* 0x00260802 */ 150 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 151 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 152 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 153 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 154 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 155 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 156 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 157 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 158 /* 0x26279222 */ 159 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 160 | (4 << TIMING_CFG2_CPO_SHIFT) \ 161 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 162 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 163 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 164 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 165 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 166 /* 0x021848c5 */ 167 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 168 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 169 /* 0x08240100 */ 170 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 171 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 172 | SDRAM_CFG_DBW_16) 173 /* 0x43100000 */ 174 175 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 176 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 177 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 178 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 179 #define CONFIG_SYS_DDR_MODE2 0x00000000 180 181 /* 182 * Memory test 183 */ 184 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 185 #define CONFIG_SYS_MEMTEST_END 0x07f00000 186 187 /* 188 * The reserved memory 189 */ 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 191 192 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 193 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 194 195 /* 196 * Initial RAM Base Address Setup 197 */ 198 #define CONFIG_SYS_INIT_RAM_LOCK 1 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 200 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 201 #define CONFIG_SYS_GBL_DATA_OFFSET \ 202 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 203 204 /* 205 * Local Bus Configuration & Clock Setup 206 */ 207 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 208 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 209 #define CONFIG_SYS_LBC_LBCR 0x00040000 210 211 /* 212 * FLASH on the Local Bus 213 */ 214 #if 1 215 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 216 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 217 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 218 #define CONFIG_FLASH_CFI_LEGACY 219 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 220 #endif 221 222 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 223 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 224 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 225 226 /* Window base at flash base */ 227 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 228 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 229 230 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 231 | BR_PS_16 /* 16 bit port */ \ 232 | BR_MS_GPCM /* MSEL = GPCM */ \ 233 | BR_V) /* valid */ 234 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 235 | OR_UPM_XAM \ 236 | OR_GPCM_CSNT \ 237 | OR_GPCM_ACS_DIV2 \ 238 | OR_GPCM_XACS \ 239 | OR_GPCM_SCY_15 \ 240 | OR_GPCM_TRLX_SET \ 241 | OR_GPCM_EHTR_SET) 242 243 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 135 245 246 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 249 /* 250 * FPGA 251 */ 252 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 253 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 254 255 /* Window base at FPGA base */ 256 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 257 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 258 259 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 260 | BR_PS_16 /* 16 bit port */ \ 261 | BR_MS_GPCM /* MSEL = GPCM */ \ 262 | BR_V) /* valid */ 263 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 264 | OR_UPM_XAM \ 265 | OR_GPCM_CSNT \ 266 | OR_GPCM_ACS_DIV2 \ 267 | OR_GPCM_XACS \ 268 | OR_GPCM_SCY_15 \ 269 | OR_GPCM_TRLX_SET \ 270 | OR_GPCM_EHTR_SET) 271 272 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 273 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 274 275 #define CONFIG_SYS_FPGA_COUNT 1 276 277 #define CONFIG_SYS_MCLINK_MAX 3 278 279 #define CONFIG_SYS_FPGA_PTR \ 280 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 281 282 /* 283 * Serial Port 284 */ 285 #define CONFIG_CONS_INDEX 2 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 289 290 #define CONFIG_SYS_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 292 293 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 294 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 295 296 /* Pass open firmware flat tree */ 297 298 /* I2C */ 299 #define CONFIG_SYS_I2C 300 #define CONFIG_SYS_I2C_FSL 301 #define CONFIG_SYS_FSL_I2C_SPEED 400000 302 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 303 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 304 305 #define CONFIG_PCA953X /* NXP PCA9554 */ 306 #define CONFIG_PCA9698 /* NXP PCA9698 */ 307 308 #define CONFIG_SYS_I2C_IHS 309 #define CONFIG_SYS_I2C_IHS_CH0 310 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 311 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 312 #define CONFIG_SYS_I2C_IHS_CH1 313 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 314 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 315 #define CONFIG_SYS_I2C_IHS_CH2 316 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 317 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 318 #define CONFIG_SYS_I2C_IHS_CH3 319 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 320 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 321 322 #ifdef CONFIG_HRCON_DH 323 #define CONFIG_SYS_I2C_IHS_DUAL 324 #define CONFIG_SYS_I2C_IHS_CH0_1 325 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 326 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 327 #define CONFIG_SYS_I2C_IHS_CH1_1 328 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 329 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 330 #define CONFIG_SYS_I2C_IHS_CH2_1 331 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 332 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 333 #define CONFIG_SYS_I2C_IHS_CH3_1 334 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 335 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 336 #endif 337 338 /* 339 * Software (bit-bang) I2C driver configuration 340 */ 341 #define CONFIG_SYS_I2C_SOFT 342 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 343 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 344 #define I2C_SOFT_DECLARATIONS2 345 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 346 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 347 #define I2C_SOFT_DECLARATIONS3 348 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 349 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 350 #define I2C_SOFT_DECLARATIONS4 351 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 353 #define I2C_SOFT_DECLARATIONS5 354 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 356 #define I2C_SOFT_DECLARATIONS6 357 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 359 #define I2C_SOFT_DECLARATIONS7 360 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 361 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 362 #define I2C_SOFT_DECLARATIONS8 363 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 364 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 365 366 #ifdef CONFIG_HRCON_DH 367 #define I2C_SOFT_DECLARATIONS9 368 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 370 #define I2C_SOFT_DECLARATIONS10 371 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 373 #define I2C_SOFT_DECLARATIONS11 374 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 375 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 376 #define I2C_SOFT_DECLARATIONS12 377 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 378 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 379 #endif 380 381 #ifdef CONFIG_HRCON_DH 382 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 383 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 384 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 385 {12, 0x4c} } 386 #else 387 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 388 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 389 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 390 {8, 0x4c} } 391 #endif 392 393 #ifndef __ASSEMBLY__ 394 void fpga_gpio_set(unsigned int bus, int pin); 395 void fpga_gpio_clear(unsigned int bus, int pin); 396 int fpga_gpio_get(unsigned int bus, int pin); 397 void fpga_control_set(unsigned int bus, int pin); 398 void fpga_control_clear(unsigned int bus, int pin); 399 #endif 400 401 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 402 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 403 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 404 405 #ifdef CONFIG_HRCON_DH 406 #define I2C_ACTIVE \ 407 do { \ 408 if (I2C_ADAP_HWNR > 7) \ 409 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 410 else \ 411 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 412 } while (0) 413 #else 414 #define I2C_ACTIVE { } 415 #endif 416 #define I2C_TRISTATE { } 417 #define I2C_READ \ 418 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 419 #define I2C_SDA(bit) \ 420 do { \ 421 if (bit) \ 422 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 423 else \ 424 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 425 } while (0) 426 #define I2C_SCL(bit) \ 427 do { \ 428 if (bit) \ 429 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 430 else \ 431 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 432 } while (0) 433 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 434 435 /* 436 * Software (bit-bang) MII driver configuration 437 */ 438 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 439 #define CONFIG_BITBANGMII_MULTI 440 441 /* 442 * OSD Setup 443 */ 444 #define CONFIG_SYS_OSD_SCREENS 1 445 #define CONFIG_SYS_DP501_DIFFERENTIAL 446 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 447 448 #ifdef CONFIG_HRCON_DH 449 #define CONFIG_SYS_OSD_DH 450 #endif 451 452 /* 453 * General PCI 454 * Addresses are mapped 1-1. 455 */ 456 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 457 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 458 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 459 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 460 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 461 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 462 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 464 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 465 466 /* enable PCIE clock */ 467 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 468 469 #define CONFIG_PCI_INDIRECT_BRIDGE 470 #define CONFIG_PCIE 471 472 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 473 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 474 475 /* 476 * TSEC 477 */ 478 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 479 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 480 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 481 482 /* 483 * TSEC ethernet configuration 484 */ 485 #define CONFIG_MII 1 /* MII PHY management */ 486 #define CONFIG_TSEC1 487 #define CONFIG_TSEC1_NAME "eTSEC0" 488 #define TSEC1_PHY_ADDR 1 489 #define TSEC1_PHYIDX 0 490 #define TSEC1_FLAGS TSEC_GIGABIT 491 492 /* Options are: eTSEC[0-1] */ 493 #define CONFIG_ETHPRIME "eTSEC0" 494 495 /* 496 * Environment 497 */ 498 #if 1 499 #define CONFIG_ENV_IS_IN_FLASH 1 500 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 501 CONFIG_SYS_MONITOR_LEN) 502 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 503 #define CONFIG_ENV_SIZE 0x2000 504 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 505 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 506 #else 507 #define CONFIG_ENV_IS_NOWHERE 508 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 509 #endif 510 511 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 512 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 513 514 /* 515 * Command line configuration. 516 */ 517 #define CONFIG_CMD_PCI 518 519 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 520 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 521 522 /* 523 * Miscellaneous configurable options 524 */ 525 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 526 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 527 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 528 529 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 530 531 /* Print Buffer Size */ 532 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 533 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 534 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 535 536 /* 537 * For booting Linux, the board info and command line data 538 * have to be in the first 256 MB of memory, since this is 539 * the maximum mapped by the Linux kernel during initialization. 540 */ 541 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 542 543 /* 544 * Core HID Setup 545 */ 546 #define CONFIG_SYS_HID0_INIT 0x000000000 547 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 548 HID0_ENABLE_INSTRUCTION_CACHE | \ 549 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 550 #define CONFIG_SYS_HID2 HID2_HBE 551 552 /* 553 * MMU Setup 554 */ 555 556 /* DDR: cache cacheable */ 557 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 558 BATL_MEMCOHERENCE) 559 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 560 BATU_VS | BATU_VP) 561 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 562 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 563 564 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 565 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 566 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 567 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 568 BATU_VP) 569 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 570 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 571 572 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 573 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 574 BATL_MEMCOHERENCE) 575 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 576 BATU_VS | BATU_VP) 577 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 578 BATL_CACHEINHIBIT | \ 579 BATL_GUARDEDSTORAGE) 580 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 581 582 /* Stack in dcache: cacheable, no memory coherence */ 583 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 584 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 585 BATU_VS | BATU_VP) 586 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 587 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 588 589 /* 590 * Environment Configuration 591 */ 592 593 #define CONFIG_ENV_OVERWRITE 594 595 #if defined(CONFIG_TSEC_ENET) 596 #define CONFIG_HAS_ETH0 597 #endif 598 599 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 600 601 602 #define CONFIG_HOSTNAME hrcon 603 #define CONFIG_ROOTPATH "/opt/nfsroot" 604 #define CONFIG_BOOTFILE "uImage" 605 606 #define CONFIG_PREBOOT /* enable preboot variable */ 607 608 #define CONFIG_EXTRA_ENV_SETTINGS \ 609 "netdev=eth0\0" \ 610 "consoledev=ttyS1\0" \ 611 "u-boot=u-boot.bin\0" \ 612 "kernel_addr=1000000\0" \ 613 "fdt_addr=C00000\0" \ 614 "fdtfile=hrcon.dtb\0" \ 615 "load=tftp ${loadaddr} ${u-boot}\0" \ 616 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 617 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 618 " +${filesize};cp.b ${fileaddr} " \ 619 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 620 "upd=run load update\0" \ 621 622 #define CONFIG_NFSBOOTCOMMAND \ 623 "setenv bootargs root=/dev/nfs rw " \ 624 "nfsroot=$serverip:$rootpath " \ 625 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 626 "console=$consoledev,$baudrate $othbootargs;" \ 627 "tftp ${kernel_addr} $bootfile;" \ 628 "tftp ${fdt_addr} $fdtfile;" \ 629 "bootm ${kernel_addr} - ${fdt_addr}" 630 631 #define CONFIG_MMCBOOTCOMMAND \ 632 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 633 "console=$consoledev,$baudrate $othbootargs;" \ 634 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 635 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 636 "bootm ${kernel_addr} - ${fdt_addr}" 637 638 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 639 640 #endif /* __CONFIG_H */ 641