1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #ifdef CONFIG_HRCON_DH 24 #define CONFIG_IDENT_STRING " hrcon dh 0.01" 25 #else 26 #define CONFIG_IDENT_STRING " hrcon 0.01" 27 #endif 28 29 #define CONFIG_BOARD_EARLY_INIT_F 30 #define CONFIG_BOARD_EARLY_INIT_R 31 #define CONFIG_LAST_STAGE_INIT 32 33 #define CONFIG_MMC 34 #define CONFIG_FSL_ESDHC 35 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 36 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 37 38 #define CONFIG_GENERIC_MMC 39 #define CONFIG_DOS_PARTITION 40 41 #define CONFIG_CMD_FPGAD 42 #define CONFIG_CMD_IOLOOP 43 44 /* 45 * System Clock Setup 46 */ 47 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 48 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 49 50 /* 51 * Hardware Reset Configuration Word 52 * if CLKIN is 66.66MHz, then 53 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 54 * We choose the A type silicon as default, so the core is 400Mhz. 55 */ 56 #define CONFIG_SYS_HRCW_LOW (\ 57 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 58 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 59 HRCWL_SVCOD_DIV_2 |\ 60 HRCWL_CSB_TO_CLKIN_4X1 |\ 61 HRCWL_CORE_TO_CSB_3X1) 62 /* 63 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 64 * in 8308's HRCWH according to the manual, but original Freescale's 65 * code has them and I've expirienced some problems using the board 66 * with BDI3000 attached when I've tried to set these bits to zero 67 * (UART doesn't work after the 'reset run' command). 68 */ 69 #define CONFIG_SYS_HRCW_HIGH (\ 70 HRCWH_PCI_HOST |\ 71 HRCWH_PCI1_ARBITER_ENABLE |\ 72 HRCWH_CORE_ENABLE |\ 73 HRCWH_FROM_0XFFF00100 |\ 74 HRCWH_BOOTSEQ_DISABLE |\ 75 HRCWH_SW_WATCHDOG_DISABLE |\ 76 HRCWH_ROM_LOC_LOCAL_16BIT |\ 77 HRCWH_RL_EXT_LEGACY |\ 78 HRCWH_TSEC1M_IN_RGMII |\ 79 HRCWH_TSEC2M_IN_RGMII |\ 80 HRCWH_BIG_ENDIAN) 81 82 /* 83 * System IO Config 84 */ 85 #define CONFIG_SYS_SICRH (\ 86 SICRH_ESDHC_A_SD |\ 87 SICRH_ESDHC_B_SD |\ 88 SICRH_ESDHC_C_SD |\ 89 SICRH_GPIO_A_GPIO |\ 90 SICRH_GPIO_B_GPIO |\ 91 SICRH_IEEE1588_A_GPIO |\ 92 SICRH_USB |\ 93 SICRH_GTM_GPIO |\ 94 SICRH_IEEE1588_B_GPIO |\ 95 SICRH_ETSEC2_GPIO |\ 96 SICRH_GPIOSEL_1 |\ 97 SICRH_TMROBI_V3P3 |\ 98 SICRH_TSOBI1_V2P5 |\ 99 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 100 #define CONFIG_SYS_SICRL (\ 101 SICRL_SPI_PF0 |\ 102 SICRL_UART_PF0 |\ 103 SICRL_IRQ_PF0 |\ 104 SICRL_I2C2_PF0 |\ 105 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 106 107 /* 108 * IMMR new address 109 */ 110 #define CONFIG_SYS_IMMR 0xE0000000 111 112 /* 113 * SERDES 114 */ 115 #define CONFIG_FSL_SERDES 116 #define CONFIG_FSL_SERDES1 0xe3000 117 118 /* 119 * Arbiter Setup 120 */ 121 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 122 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 123 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 124 125 /* 126 * DDR Setup 127 */ 128 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 130 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 131 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 132 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 133 | DDRCDR_PZ_LOZ \ 134 | DDRCDR_NZ_LOZ \ 135 | DDRCDR_ODT \ 136 | DDRCDR_Q_DRN) 137 /* 0x7b880001 */ 138 /* 139 * Manually set up DDR parameters 140 * consist of one chip NT5TU64M16HG from NANYA 141 */ 142 143 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 144 145 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 146 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 147 | CSCONFIG_ODT_RD_NEVER \ 148 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 149 | CSCONFIG_BANK_BIT_3 \ 150 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 151 /* 0x80010102 */ 152 #define CONFIG_SYS_DDR_TIMING_3 0 153 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 154 | (0 << TIMING_CFG0_WRT_SHIFT) \ 155 | (0 << TIMING_CFG0_RRT_SHIFT) \ 156 | (0 << TIMING_CFG0_WWT_SHIFT) \ 157 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 158 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 159 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 160 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 161 /* 0x00260802 */ 162 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 163 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 164 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 165 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 166 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 167 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 168 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 169 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 170 /* 0x26279222 */ 171 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 172 | (4 << TIMING_CFG2_CPO_SHIFT) \ 173 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 174 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 175 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 176 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 177 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 178 /* 0x021848c5 */ 179 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 180 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 181 /* 0x08240100 */ 182 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 183 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 184 | SDRAM_CFG_DBW_16) 185 /* 0x43100000 */ 186 187 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 188 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 189 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 190 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 191 #define CONFIG_SYS_DDR_MODE2 0x00000000 192 193 /* 194 * Memory test 195 */ 196 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 197 #define CONFIG_SYS_MEMTEST_END 0x07f00000 198 199 /* 200 * The reserved memory 201 */ 202 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 203 204 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 205 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 206 207 /* 208 * Initial RAM Base Address Setup 209 */ 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 213 #define CONFIG_SYS_GBL_DATA_OFFSET \ 214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 216 /* 217 * Local Bus Configuration & Clock Setup 218 */ 219 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 220 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 221 #define CONFIG_SYS_LBC_LBCR 0x00040000 222 223 /* 224 * FLASH on the Local Bus 225 */ 226 #if 1 227 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 228 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 229 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 230 #define CONFIG_FLASH_CFI_LEGACY 231 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 232 #else 233 #define CONFIG_SYS_NO_FLASH 234 #endif 235 236 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 237 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 238 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 239 240 /* Window base at flash base */ 241 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 242 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 243 244 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 245 | BR_PS_16 /* 16 bit port */ \ 246 | BR_MS_GPCM /* MSEL = GPCM */ \ 247 | BR_V) /* valid */ 248 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 249 | OR_UPM_XAM \ 250 | OR_GPCM_CSNT \ 251 | OR_GPCM_ACS_DIV2 \ 252 | OR_GPCM_XACS \ 253 | OR_GPCM_SCY_15 \ 254 | OR_GPCM_TRLX_SET \ 255 | OR_GPCM_EHTR_SET) 256 257 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 258 #define CONFIG_SYS_MAX_FLASH_SECT 135 259 260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 262 263 /* 264 * FPGA 265 */ 266 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 267 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 268 269 /* Window base at FPGA base */ 270 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 271 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 272 273 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 274 | BR_PS_16 /* 16 bit port */ \ 275 | BR_MS_GPCM /* MSEL = GPCM */ \ 276 | BR_V) /* valid */ 277 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 278 | OR_UPM_XAM \ 279 | OR_GPCM_CSNT \ 280 | OR_GPCM_ACS_DIV2 \ 281 | OR_GPCM_XACS \ 282 | OR_GPCM_SCY_15 \ 283 | OR_GPCM_TRLX_SET \ 284 | OR_GPCM_EHTR_SET) 285 286 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 287 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 288 289 #define CONFIG_SYS_FPGA_COUNT 1 290 291 #define CONFIG_SYS_MCLINK_MAX 3 292 293 #define CONFIG_SYS_FPGA_PTR \ 294 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 295 296 /* 297 * Serial Port 298 */ 299 #define CONFIG_CONS_INDEX 2 300 #define CONFIG_SYS_NS16550_SERIAL 301 #define CONFIG_SYS_NS16550_REG_SIZE 1 302 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 303 304 #define CONFIG_SYS_BAUDRATE_TABLE \ 305 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 306 307 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 308 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 309 310 /* Pass open firmware flat tree */ 311 312 /* I2C */ 313 #define CONFIG_SYS_I2C 314 #define CONFIG_SYS_I2C_FSL 315 #define CONFIG_SYS_FSL_I2C_SPEED 400000 316 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 317 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 318 319 #define CONFIG_PCA953X /* NXP PCA9554 */ 320 #define CONFIG_PCA9698 /* NXP PCA9698 */ 321 322 #define CONFIG_SYS_I2C_IHS 323 #define CONFIG_SYS_I2C_IHS_CH0 324 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 325 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 326 #define CONFIG_SYS_I2C_IHS_CH1 327 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 328 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 329 #define CONFIG_SYS_I2C_IHS_CH2 330 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 331 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 332 #define CONFIG_SYS_I2C_IHS_CH3 333 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 334 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 335 336 #ifdef CONFIG_HRCON_DH 337 #define CONFIG_SYS_I2C_IHS_DUAL 338 #define CONFIG_SYS_I2C_IHS_CH0_1 339 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 340 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 341 #define CONFIG_SYS_I2C_IHS_CH1_1 342 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 343 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 344 #define CONFIG_SYS_I2C_IHS_CH2_1 345 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 346 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 347 #define CONFIG_SYS_I2C_IHS_CH3_1 348 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 349 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 350 #endif 351 352 /* 353 * Software (bit-bang) I2C driver configuration 354 */ 355 #define CONFIG_SYS_I2C_SOFT 356 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 357 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 358 #define I2C_SOFT_DECLARATIONS2 359 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 360 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 361 #define I2C_SOFT_DECLARATIONS3 362 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 364 #define I2C_SOFT_DECLARATIONS4 365 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 367 #define I2C_SOFT_DECLARATIONS5 368 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 370 #define I2C_SOFT_DECLARATIONS6 371 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 373 #define I2C_SOFT_DECLARATIONS7 374 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 375 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 376 #define I2C_SOFT_DECLARATIONS8 377 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 378 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 379 380 #ifdef CONFIG_HRCON_DH 381 #define I2C_SOFT_DECLARATIONS9 382 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 383 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 384 #define I2C_SOFT_DECLARATIONS10 385 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 386 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 387 #define I2C_SOFT_DECLARATIONS11 388 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 389 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 390 #define I2C_SOFT_DECLARATIONS12 391 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 392 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 393 #endif 394 395 #ifdef CONFIG_HRCON_DH 396 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 397 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 398 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 399 {12, 0x4c} } 400 #else 401 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 402 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 403 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 404 {8, 0x4c} } 405 #endif 406 407 #ifndef __ASSEMBLY__ 408 void fpga_gpio_set(unsigned int bus, int pin); 409 void fpga_gpio_clear(unsigned int bus, int pin); 410 int fpga_gpio_get(unsigned int bus, int pin); 411 void fpga_control_set(unsigned int bus, int pin); 412 void fpga_control_clear(unsigned int bus, int pin); 413 #endif 414 415 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 416 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 417 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 418 419 #ifdef CONFIG_HRCON_DH 420 #define I2C_ACTIVE \ 421 do { \ 422 if (I2C_ADAP_HWNR > 7) \ 423 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 424 else \ 425 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 426 } while (0) 427 #else 428 #define I2C_ACTIVE { } 429 #endif 430 #define I2C_TRISTATE { } 431 #define I2C_READ \ 432 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 433 #define I2C_SDA(bit) \ 434 do { \ 435 if (bit) \ 436 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 437 else \ 438 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 439 } while (0) 440 #define I2C_SCL(bit) \ 441 do { \ 442 if (bit) \ 443 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 444 else \ 445 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 446 } while (0) 447 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 448 449 /* 450 * Software (bit-bang) MII driver configuration 451 */ 452 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 453 #define CONFIG_BITBANGMII_MULTI 454 455 /* 456 * OSD Setup 457 */ 458 #define CONFIG_SYS_OSD_SCREENS 1 459 #define CONFIG_SYS_DP501_DIFFERENTIAL 460 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 461 462 #ifdef CONFIG_HRCON_DH 463 #define CONFIG_SYS_OSD_DH 464 #endif 465 466 /* 467 * General PCI 468 * Addresses are mapped 1-1. 469 */ 470 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 471 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 472 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 473 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 474 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 475 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 476 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 478 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 479 480 /* enable PCIE clock */ 481 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 482 483 #define CONFIG_PCI 484 #define CONFIG_PCI_INDIRECT_BRIDGE 485 #define CONFIG_PCIE 486 487 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 488 489 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 490 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 491 492 /* 493 * TSEC 494 */ 495 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 496 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 497 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 498 499 /* 500 * TSEC ethernet configuration 501 */ 502 #define CONFIG_MII 1 /* MII PHY management */ 503 #define CONFIG_TSEC1 504 #define CONFIG_TSEC1_NAME "eTSEC0" 505 #define TSEC1_PHY_ADDR 1 506 #define TSEC1_PHYIDX 0 507 #define TSEC1_FLAGS TSEC_GIGABIT 508 509 /* Options are: eTSEC[0-1] */ 510 #define CONFIG_ETHPRIME "eTSEC0" 511 512 /* 513 * Environment 514 */ 515 #if 1 516 #define CONFIG_ENV_IS_IN_FLASH 1 517 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 518 CONFIG_SYS_MONITOR_LEN) 519 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 520 #define CONFIG_ENV_SIZE 0x2000 521 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 522 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 523 #else 524 #define CONFIG_ENV_IS_NOWHERE 525 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 526 #endif 527 528 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 529 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 530 531 /* 532 * Command line configuration. 533 */ 534 #define CONFIG_CMD_PCI 535 536 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 537 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 538 539 /* 540 * Miscellaneous configurable options 541 */ 542 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 543 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 544 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 545 546 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 547 548 #define CONFIG_SYS_CONSOLE_INFO_QUIET 549 550 /* Print Buffer Size */ 551 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 552 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 553 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 554 555 /* 556 * For booting Linux, the board info and command line data 557 * have to be in the first 256 MB of memory, since this is 558 * the maximum mapped by the Linux kernel during initialization. 559 */ 560 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 561 562 /* 563 * Core HID Setup 564 */ 565 #define CONFIG_SYS_HID0_INIT 0x000000000 566 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 567 HID0_ENABLE_INSTRUCTION_CACHE | \ 568 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 569 #define CONFIG_SYS_HID2 HID2_HBE 570 571 /* 572 * MMU Setup 573 */ 574 575 /* DDR: cache cacheable */ 576 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 577 BATL_MEMCOHERENCE) 578 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 579 BATU_VS | BATU_VP) 580 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 581 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 582 583 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 584 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 585 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 586 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 587 BATU_VP) 588 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 589 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 590 591 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 592 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 593 BATL_MEMCOHERENCE) 594 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 595 BATU_VS | BATU_VP) 596 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 597 BATL_CACHEINHIBIT | \ 598 BATL_GUARDEDSTORAGE) 599 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 600 601 /* Stack in dcache: cacheable, no memory coherence */ 602 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 603 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 604 BATU_VS | BATU_VP) 605 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 606 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 607 608 /* 609 * Environment Configuration 610 */ 611 612 #define CONFIG_ENV_OVERWRITE 613 614 #if defined(CONFIG_TSEC_ENET) 615 #define CONFIG_HAS_ETH0 616 #endif 617 618 #define CONFIG_BAUDRATE 115200 619 620 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 621 622 623 #define CONFIG_HOSTNAME hrcon 624 #define CONFIG_ROOTPATH "/opt/nfsroot" 625 #define CONFIG_BOOTFILE "uImage" 626 627 #define CONFIG_PREBOOT /* enable preboot variable */ 628 629 #define CONFIG_EXTRA_ENV_SETTINGS \ 630 "netdev=eth0\0" \ 631 "consoledev=ttyS1\0" \ 632 "u-boot=u-boot.bin\0" \ 633 "kernel_addr=1000000\0" \ 634 "fdt_addr=C00000\0" \ 635 "fdtfile=hrcon.dtb\0" \ 636 "load=tftp ${loadaddr} ${u-boot}\0" \ 637 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 638 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 639 " +${filesize};cp.b ${fileaddr} " \ 640 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 641 "upd=run load update\0" \ 642 643 #define CONFIG_NFSBOOTCOMMAND \ 644 "setenv bootargs root=/dev/nfs rw " \ 645 "nfsroot=$serverip:$rootpath " \ 646 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 647 "console=$consoledev,$baudrate $othbootargs;" \ 648 "tftp ${kernel_addr} $bootfile;" \ 649 "tftp ${fdt_addr} $fdtfile;" \ 650 "bootm ${kernel_addr} - ${fdt_addr}" 651 652 #define CONFIG_MMCBOOTCOMMAND \ 653 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 654 "console=$consoledev,$baudrate $othbootargs;" \ 655 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 656 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 657 "bootm ${kernel_addr} - ${fdt_addr}" 658 659 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 660 661 #endif /* __CONFIG_H */ 662