1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_FSL_ESDHC 22 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 23 24 /* 25 * System Clock Setup 26 */ 27 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 28 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 29 30 /* 31 * Hardware Reset Configuration Word 32 * if CLKIN is 66.66MHz, then 33 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 34 * We choose the A type silicon as default, so the core is 400Mhz. 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 39 HRCWL_SVCOD_DIV_2 |\ 40 HRCWL_CSB_TO_CLKIN_4X1 |\ 41 HRCWL_CORE_TO_CSB_3X1) 42 /* 43 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 44 * in 8308's HRCWH according to the manual, but original Freescale's 45 * code has them and I've expirienced some problems using the board 46 * with BDI3000 attached when I've tried to set these bits to zero 47 * (UART doesn't work after the 'reset run' command). 48 */ 49 #define CONFIG_SYS_HRCW_HIGH (\ 50 HRCWH_PCI_HOST |\ 51 HRCWH_PCI1_ARBITER_ENABLE |\ 52 HRCWH_CORE_ENABLE |\ 53 HRCWH_FROM_0XFFF00100 |\ 54 HRCWH_BOOTSEQ_DISABLE |\ 55 HRCWH_SW_WATCHDOG_DISABLE |\ 56 HRCWH_ROM_LOC_LOCAL_16BIT |\ 57 HRCWH_RL_EXT_LEGACY |\ 58 HRCWH_TSEC1M_IN_RGMII |\ 59 HRCWH_TSEC2M_IN_RGMII |\ 60 HRCWH_BIG_ENDIAN) 61 62 /* 63 * System IO Config 64 */ 65 #define CONFIG_SYS_SICRH (\ 66 SICRH_ESDHC_A_SD |\ 67 SICRH_ESDHC_B_SD |\ 68 SICRH_ESDHC_C_SD |\ 69 SICRH_GPIO_A_GPIO |\ 70 SICRH_GPIO_B_GPIO |\ 71 SICRH_IEEE1588_A_GPIO |\ 72 SICRH_USB |\ 73 SICRH_GTM_GPIO |\ 74 SICRH_IEEE1588_B_GPIO |\ 75 SICRH_ETSEC2_GPIO |\ 76 SICRH_GPIOSEL_1 |\ 77 SICRH_TMROBI_V3P3 |\ 78 SICRH_TSOBI1_V2P5 |\ 79 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 80 #define CONFIG_SYS_SICRL (\ 81 SICRL_SPI_PF0 |\ 82 SICRL_UART_PF0 |\ 83 SICRL_IRQ_PF0 |\ 84 SICRL_I2C2_PF0 |\ 85 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 86 87 /* 88 * IMMR new address 89 */ 90 #define CONFIG_SYS_IMMR 0xE0000000 91 92 /* 93 * SERDES 94 */ 95 #define CONFIG_FSL_SERDES 96 #define CONFIG_FSL_SERDES1 0xe3000 97 98 /* 99 * Arbiter Setup 100 */ 101 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 102 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 103 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 104 105 /* 106 * DDR Setup 107 */ 108 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 110 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 112 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 113 | DDRCDR_PZ_LOZ \ 114 | DDRCDR_NZ_LOZ \ 115 | DDRCDR_ODT \ 116 | DDRCDR_Q_DRN) 117 /* 0x7b880001 */ 118 /* 119 * Manually set up DDR parameters 120 * consist of one chip NT5TU64M16HG from NANYA 121 */ 122 123 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 124 125 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 126 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 127 | CSCONFIG_ODT_RD_NEVER \ 128 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 129 | CSCONFIG_BANK_BIT_3 \ 130 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 131 /* 0x80010102 */ 132 #define CONFIG_SYS_DDR_TIMING_3 0 133 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 134 | (0 << TIMING_CFG0_WRT_SHIFT) \ 135 | (0 << TIMING_CFG0_RRT_SHIFT) \ 136 | (0 << TIMING_CFG0_WWT_SHIFT) \ 137 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 138 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 139 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 140 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 141 /* 0x00260802 */ 142 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 143 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 144 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 145 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 146 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 147 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 148 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 149 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 150 /* 0x26279222 */ 151 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 152 | (4 << TIMING_CFG2_CPO_SHIFT) \ 153 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 154 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 155 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 156 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 157 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 158 /* 0x021848c5 */ 159 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 160 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 161 /* 0x08240100 */ 162 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 163 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 164 | SDRAM_CFG_DBW_16) 165 /* 0x43100000 */ 166 167 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 168 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 169 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 170 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 171 #define CONFIG_SYS_DDR_MODE2 0x00000000 172 173 /* 174 * Memory test 175 */ 176 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 177 #define CONFIG_SYS_MEMTEST_END 0x07f00000 178 179 /* 180 * The reserved memory 181 */ 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 183 184 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 185 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 186 187 /* 188 * Initial RAM Base Address Setup 189 */ 190 #define CONFIG_SYS_INIT_RAM_LOCK 1 191 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 192 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 193 #define CONFIG_SYS_GBL_DATA_OFFSET \ 194 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 195 196 /* 197 * Local Bus Configuration & Clock Setup 198 */ 199 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 200 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 201 #define CONFIG_SYS_LBC_LBCR 0x00040000 202 203 /* 204 * FLASH on the Local Bus 205 */ 206 #if 1 207 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 208 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 209 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 210 #define CONFIG_FLASH_CFI_LEGACY 211 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 212 #endif 213 214 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 215 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 216 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 217 218 /* Window base at flash base */ 219 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 220 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 221 222 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 223 | BR_PS_16 /* 16 bit port */ \ 224 | BR_MS_GPCM /* MSEL = GPCM */ \ 225 | BR_V) /* valid */ 226 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 227 | OR_UPM_XAM \ 228 | OR_GPCM_CSNT \ 229 | OR_GPCM_ACS_DIV2 \ 230 | OR_GPCM_XACS \ 231 | OR_GPCM_SCY_15 \ 232 | OR_GPCM_TRLX_SET \ 233 | OR_GPCM_EHTR_SET) 234 235 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 236 #define CONFIG_SYS_MAX_FLASH_SECT 135 237 238 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 239 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 240 241 /* 242 * FPGA 243 */ 244 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 245 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 246 247 /* Window base at FPGA base */ 248 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 249 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 250 251 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 252 | BR_PS_16 /* 16 bit port */ \ 253 | BR_MS_GPCM /* MSEL = GPCM */ \ 254 | BR_V) /* valid */ 255 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 256 | OR_UPM_XAM \ 257 | OR_GPCM_CSNT \ 258 | OR_GPCM_ACS_DIV2 \ 259 | OR_GPCM_XACS \ 260 | OR_GPCM_SCY_15 \ 261 | OR_GPCM_TRLX_SET \ 262 | OR_GPCM_EHTR_SET) 263 264 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 265 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 266 267 #define CONFIG_SYS_FPGA_COUNT 1 268 269 #define CONFIG_SYS_MCLINK_MAX 3 270 271 #define CONFIG_SYS_FPGA_PTR \ 272 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 273 274 /* 275 * Serial Port 276 */ 277 #define CONFIG_SYS_NS16550_SERIAL 278 #define CONFIG_SYS_NS16550_REG_SIZE 1 279 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 280 281 #define CONFIG_SYS_BAUDRATE_TABLE \ 282 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 283 284 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 285 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 286 287 /* Pass open firmware flat tree */ 288 289 /* I2C */ 290 #define CONFIG_SYS_I2C 291 #define CONFIG_SYS_I2C_FSL 292 #define CONFIG_SYS_FSL_I2C_SPEED 400000 293 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 294 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 295 296 #define CONFIG_PCA953X /* NXP PCA9554 */ 297 #define CONFIG_PCA9698 /* NXP PCA9698 */ 298 299 #define CONFIG_SYS_I2C_IHS 300 #define CONFIG_SYS_I2C_IHS_CH0 301 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 302 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 303 #define CONFIG_SYS_I2C_IHS_CH1 304 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 305 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 306 #define CONFIG_SYS_I2C_IHS_CH2 307 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 308 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 309 #define CONFIG_SYS_I2C_IHS_CH3 310 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 311 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 312 313 #ifdef CONFIG_HRCON_DH 314 #define CONFIG_SYS_I2C_IHS_DUAL 315 #define CONFIG_SYS_I2C_IHS_CH0_1 316 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 317 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 318 #define CONFIG_SYS_I2C_IHS_CH1_1 319 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 320 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 321 #define CONFIG_SYS_I2C_IHS_CH2_1 322 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 323 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 324 #define CONFIG_SYS_I2C_IHS_CH3_1 325 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 326 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 327 #endif 328 329 /* 330 * Software (bit-bang) I2C driver configuration 331 */ 332 #define CONFIG_SYS_I2C_SOFT 333 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 334 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 335 #define I2C_SOFT_DECLARATIONS2 336 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 337 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 338 #define I2C_SOFT_DECLARATIONS3 339 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 340 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 341 #define I2C_SOFT_DECLARATIONS4 342 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 343 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 344 #define I2C_SOFT_DECLARATIONS5 345 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 346 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 347 #define I2C_SOFT_DECLARATIONS6 348 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 349 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 350 #define I2C_SOFT_DECLARATIONS7 351 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 353 #define I2C_SOFT_DECLARATIONS8 354 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 356 357 #ifdef CONFIG_HRCON_DH 358 #define I2C_SOFT_DECLARATIONS9 359 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 360 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 361 #define I2C_SOFT_DECLARATIONS10 362 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 364 #define I2C_SOFT_DECLARATIONS11 365 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 367 #define I2C_SOFT_DECLARATIONS12 368 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 370 #endif 371 372 #ifdef CONFIG_HRCON_DH 373 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 374 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 375 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 376 {12, 0x4c} } 377 #else 378 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 379 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 380 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 381 {8, 0x4c} } 382 #endif 383 384 #ifndef __ASSEMBLY__ 385 void fpga_gpio_set(unsigned int bus, int pin); 386 void fpga_gpio_clear(unsigned int bus, int pin); 387 int fpga_gpio_get(unsigned int bus, int pin); 388 void fpga_control_set(unsigned int bus, int pin); 389 void fpga_control_clear(unsigned int bus, int pin); 390 #endif 391 392 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 393 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 394 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 395 396 #ifdef CONFIG_HRCON_DH 397 #define I2C_ACTIVE \ 398 do { \ 399 if (I2C_ADAP_HWNR > 7) \ 400 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 401 else \ 402 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 403 } while (0) 404 #else 405 #define I2C_ACTIVE { } 406 #endif 407 #define I2C_TRISTATE { } 408 #define I2C_READ \ 409 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 410 #define I2C_SDA(bit) \ 411 do { \ 412 if (bit) \ 413 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 414 else \ 415 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 416 } while (0) 417 #define I2C_SCL(bit) \ 418 do { \ 419 if (bit) \ 420 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 421 else \ 422 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 423 } while (0) 424 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 425 426 /* 427 * Software (bit-bang) MII driver configuration 428 */ 429 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 430 #define CONFIG_BITBANGMII_MULTI 431 432 /* 433 * OSD Setup 434 */ 435 #define CONFIG_SYS_OSD_SCREENS 1 436 #define CONFIG_SYS_DP501_DIFFERENTIAL 437 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 438 439 #ifdef CONFIG_HRCON_DH 440 #define CONFIG_SYS_OSD_DH 441 #endif 442 443 /* 444 * General PCI 445 * Addresses are mapped 1-1. 446 */ 447 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 448 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 449 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 450 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 451 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 452 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 453 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 454 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 455 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 456 457 /* enable PCIE clock */ 458 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 459 460 #define CONFIG_PCI_INDIRECT_BRIDGE 461 #define CONFIG_PCIE 462 463 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 464 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 465 466 /* 467 * TSEC 468 */ 469 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 470 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 471 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 472 473 /* 474 * TSEC ethernet configuration 475 */ 476 #define CONFIG_MII 1 /* MII PHY management */ 477 #define CONFIG_TSEC1 478 #define CONFIG_TSEC1_NAME "eTSEC0" 479 #define TSEC1_PHY_ADDR 1 480 #define TSEC1_PHYIDX 0 481 #define TSEC1_FLAGS TSEC_GIGABIT 482 483 /* Options are: eTSEC[0-1] */ 484 #define CONFIG_ETHPRIME "eTSEC0" 485 486 /* 487 * Environment 488 */ 489 #if 1 490 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 491 CONFIG_SYS_MONITOR_LEN) 492 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 493 #define CONFIG_ENV_SIZE 0x2000 494 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 495 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 496 #else 497 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 498 #endif 499 500 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 501 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 502 503 /* 504 * Command line configuration. 505 */ 506 507 /* 508 * Miscellaneous configurable options 509 */ 510 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 511 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 512 513 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 514 515 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 516 517 /* 518 * For booting Linux, the board info and command line data 519 * have to be in the first 256 MB of memory, since this is 520 * the maximum mapped by the Linux kernel during initialization. 521 */ 522 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 523 524 /* 525 * Core HID Setup 526 */ 527 #define CONFIG_SYS_HID0_INIT 0x000000000 528 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 529 HID0_ENABLE_INSTRUCTION_CACHE | \ 530 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 531 #define CONFIG_SYS_HID2 HID2_HBE 532 533 /* 534 * MMU Setup 535 */ 536 537 /* DDR: cache cacheable */ 538 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 539 BATL_MEMCOHERENCE) 540 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 541 BATU_VS | BATU_VP) 542 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 543 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 544 545 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 546 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 547 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 548 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 549 BATU_VP) 550 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 551 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 552 553 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 554 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 555 BATL_MEMCOHERENCE) 556 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 557 BATU_VS | BATU_VP) 558 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 559 BATL_CACHEINHIBIT | \ 560 BATL_GUARDEDSTORAGE) 561 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 562 563 /* Stack in dcache: cacheable, no memory coherence */ 564 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 565 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 566 BATU_VS | BATU_VP) 567 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 568 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 569 570 /* 571 * Environment Configuration 572 */ 573 574 #define CONFIG_ENV_OVERWRITE 575 576 #if defined(CONFIG_TSEC_ENET) 577 #define CONFIG_HAS_ETH0 578 #endif 579 580 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 581 582 583 #define CONFIG_HOSTNAME hrcon 584 #define CONFIG_ROOTPATH "/opt/nfsroot" 585 #define CONFIG_BOOTFILE "uImage" 586 587 #define CONFIG_PREBOOT /* enable preboot variable */ 588 589 #define CONFIG_EXTRA_ENV_SETTINGS \ 590 "netdev=eth0\0" \ 591 "consoledev=ttyS1\0" \ 592 "u-boot=u-boot.bin\0" \ 593 "kernel_addr=1000000\0" \ 594 "fdt_addr=C00000\0" \ 595 "fdtfile=hrcon.dtb\0" \ 596 "load=tftp ${loadaddr} ${u-boot}\0" \ 597 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 598 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 599 " +${filesize};cp.b ${fileaddr} " \ 600 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 601 "upd=run load update\0" \ 602 603 #define CONFIG_NFSBOOTCOMMAND \ 604 "setenv bootargs root=/dev/nfs rw " \ 605 "nfsroot=$serverip:$rootpath " \ 606 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 607 "console=$consoledev,$baudrate $othbootargs;" \ 608 "tftp ${kernel_addr} $bootfile;" \ 609 "tftp ${fdt_addr} $fdtfile;" \ 610 "bootm ${kernel_addr} - ${fdt_addr}" 611 612 #define CONFIG_MMCBOOTCOMMAND \ 613 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 616 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 617 "bootm ${kernel_addr} - ${fdt_addr}" 618 619 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 620 621 #endif /* __CONFIG_H */ 622