1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_HRCON 1 /* HRCON board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_R 24 #define CONFIG_LAST_STAGE_INIT 25 26 #define CONFIG_FSL_ESDHC 27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 28 29 #define CONFIG_GENERIC_MMC 30 #define CONFIG_DOS_PARTITION 31 32 #define CONFIG_CMD_FPGAD 33 #define CONFIG_CMD_IOLOOP 34 35 /* 36 * System Clock Setup 37 */ 38 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 39 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 40 41 /* 42 * Hardware Reset Configuration Word 43 * if CLKIN is 66.66MHz, then 44 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 45 * We choose the A type silicon as default, so the core is 400Mhz. 46 */ 47 #define CONFIG_SYS_HRCW_LOW (\ 48 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 50 HRCWL_SVCOD_DIV_2 |\ 51 HRCWL_CSB_TO_CLKIN_4X1 |\ 52 HRCWL_CORE_TO_CSB_3X1) 53 /* 54 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 55 * in 8308's HRCWH according to the manual, but original Freescale's 56 * code has them and I've expirienced some problems using the board 57 * with BDI3000 attached when I've tried to set these bits to zero 58 * (UART doesn't work after the 'reset run' command). 59 */ 60 #define CONFIG_SYS_HRCW_HIGH (\ 61 HRCWH_PCI_HOST |\ 62 HRCWH_PCI1_ARBITER_ENABLE |\ 63 HRCWH_CORE_ENABLE |\ 64 HRCWH_FROM_0XFFF00100 |\ 65 HRCWH_BOOTSEQ_DISABLE |\ 66 HRCWH_SW_WATCHDOG_DISABLE |\ 67 HRCWH_ROM_LOC_LOCAL_16BIT |\ 68 HRCWH_RL_EXT_LEGACY |\ 69 HRCWH_TSEC1M_IN_RGMII |\ 70 HRCWH_TSEC2M_IN_RGMII |\ 71 HRCWH_BIG_ENDIAN) 72 73 /* 74 * System IO Config 75 */ 76 #define CONFIG_SYS_SICRH (\ 77 SICRH_ESDHC_A_SD |\ 78 SICRH_ESDHC_B_SD |\ 79 SICRH_ESDHC_C_SD |\ 80 SICRH_GPIO_A_GPIO |\ 81 SICRH_GPIO_B_GPIO |\ 82 SICRH_IEEE1588_A_GPIO |\ 83 SICRH_USB |\ 84 SICRH_GTM_GPIO |\ 85 SICRH_IEEE1588_B_GPIO |\ 86 SICRH_ETSEC2_GPIO |\ 87 SICRH_GPIOSEL_1 |\ 88 SICRH_TMROBI_V3P3 |\ 89 SICRH_TSOBI1_V2P5 |\ 90 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 91 #define CONFIG_SYS_SICRL (\ 92 SICRL_SPI_PF0 |\ 93 SICRL_UART_PF0 |\ 94 SICRL_IRQ_PF0 |\ 95 SICRL_I2C2_PF0 |\ 96 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */ 97 98 /* 99 * IMMR new address 100 */ 101 #define CONFIG_SYS_IMMR 0xE0000000 102 103 /* 104 * SERDES 105 */ 106 #define CONFIG_FSL_SERDES 107 #define CONFIG_FSL_SERDES1 0xe3000 108 109 /* 110 * Arbiter Setup 111 */ 112 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 113 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 114 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 115 116 /* 117 * DDR Setup 118 */ 119 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 121 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 122 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 123 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 124 | DDRCDR_PZ_LOZ \ 125 | DDRCDR_NZ_LOZ \ 126 | DDRCDR_ODT \ 127 | DDRCDR_Q_DRN) 128 /* 0x7b880001 */ 129 /* 130 * Manually set up DDR parameters 131 * consist of one chip NT5TU64M16HG from NANYA 132 */ 133 134 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 135 136 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 137 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 138 | CSCONFIG_ODT_RD_NEVER \ 139 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 140 | CSCONFIG_BANK_BIT_3 \ 141 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 142 /* 0x80010102 */ 143 #define CONFIG_SYS_DDR_TIMING_3 0 144 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 145 | (0 << TIMING_CFG0_WRT_SHIFT) \ 146 | (0 << TIMING_CFG0_RRT_SHIFT) \ 147 | (0 << TIMING_CFG0_WWT_SHIFT) \ 148 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 149 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 150 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 151 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 152 /* 0x00260802 */ 153 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 154 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 156 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 157 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 158 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 159 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 160 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 161 /* 0x26279222 */ 162 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 163 | (4 << TIMING_CFG2_CPO_SHIFT) \ 164 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 165 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 166 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 167 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 168 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 169 /* 0x021848c5 */ 170 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 171 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 172 /* 0x08240100 */ 173 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 174 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 175 | SDRAM_CFG_DBW_16) 176 /* 0x43100000 */ 177 178 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 179 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 180 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 181 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 182 #define CONFIG_SYS_DDR_MODE2 0x00000000 183 184 /* 185 * Memory test 186 */ 187 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 188 #define CONFIG_SYS_MEMTEST_END 0x07f00000 189 190 /* 191 * The reserved memory 192 */ 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 194 195 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 196 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 197 198 /* 199 * Initial RAM Base Address Setup 200 */ 201 #define CONFIG_SYS_INIT_RAM_LOCK 1 202 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 203 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 204 #define CONFIG_SYS_GBL_DATA_OFFSET \ 205 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 206 207 /* 208 * Local Bus Configuration & Clock Setup 209 */ 210 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 211 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 212 #define CONFIG_SYS_LBC_LBCR 0x00040000 213 214 /* 215 * FLASH on the Local Bus 216 */ 217 #if 1 218 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 219 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 220 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 221 #define CONFIG_FLASH_CFI_LEGACY 222 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 223 #else 224 #define CONFIG_SYS_NO_FLASH 225 #endif 226 227 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 228 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 229 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 230 231 /* Window base at flash base */ 232 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 233 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 234 235 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 236 | BR_PS_16 /* 16 bit port */ \ 237 | BR_MS_GPCM /* MSEL = GPCM */ \ 238 | BR_V) /* valid */ 239 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 240 | OR_UPM_XAM \ 241 | OR_GPCM_CSNT \ 242 | OR_GPCM_ACS_DIV2 \ 243 | OR_GPCM_XACS \ 244 | OR_GPCM_SCY_15 \ 245 | OR_GPCM_TRLX_SET \ 246 | OR_GPCM_EHTR_SET) 247 248 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 249 #define CONFIG_SYS_MAX_FLASH_SECT 135 250 251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 253 254 /* 255 * FPGA 256 */ 257 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 258 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 259 260 /* Window base at FPGA base */ 261 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 262 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 263 264 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 265 | BR_PS_16 /* 16 bit port */ \ 266 | BR_MS_GPCM /* MSEL = GPCM */ \ 267 | BR_V) /* valid */ 268 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 269 | OR_UPM_XAM \ 270 | OR_GPCM_CSNT \ 271 | OR_GPCM_ACS_DIV2 \ 272 | OR_GPCM_XACS \ 273 | OR_GPCM_SCY_15 \ 274 | OR_GPCM_TRLX_SET \ 275 | OR_GPCM_EHTR_SET) 276 277 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 278 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 279 280 #define CONFIG_SYS_FPGA_COUNT 1 281 282 #define CONFIG_SYS_MCLINK_MAX 3 283 284 #define CONFIG_SYS_FPGA_PTR \ 285 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 286 287 /* 288 * Serial Port 289 */ 290 #define CONFIG_CONS_INDEX 2 291 #define CONFIG_SYS_NS16550_SERIAL 292 #define CONFIG_SYS_NS16550_REG_SIZE 1 293 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 294 295 #define CONFIG_SYS_BAUDRATE_TABLE \ 296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 297 298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 300 301 /* Pass open firmware flat tree */ 302 303 /* I2C */ 304 #define CONFIG_SYS_I2C 305 #define CONFIG_SYS_I2C_FSL 306 #define CONFIG_SYS_FSL_I2C_SPEED 400000 307 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 308 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 309 310 #define CONFIG_PCA953X /* NXP PCA9554 */ 311 #define CONFIG_PCA9698 /* NXP PCA9698 */ 312 313 #define CONFIG_SYS_I2C_IHS 314 #define CONFIG_SYS_I2C_IHS_CH0 315 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 316 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 317 #define CONFIG_SYS_I2C_IHS_CH1 318 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 319 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 320 #define CONFIG_SYS_I2C_IHS_CH2 321 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 322 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 323 #define CONFIG_SYS_I2C_IHS_CH3 324 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 325 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 326 327 #ifdef CONFIG_HRCON_DH 328 #define CONFIG_SYS_I2C_IHS_DUAL 329 #define CONFIG_SYS_I2C_IHS_CH0_1 330 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 331 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 332 #define CONFIG_SYS_I2C_IHS_CH1_1 333 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 334 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 335 #define CONFIG_SYS_I2C_IHS_CH2_1 336 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 337 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 338 #define CONFIG_SYS_I2C_IHS_CH3_1 339 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 340 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 341 #endif 342 343 /* 344 * Software (bit-bang) I2C driver configuration 345 */ 346 #define CONFIG_SYS_I2C_SOFT 347 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 348 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 349 #define I2C_SOFT_DECLARATIONS2 350 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 351 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 352 #define I2C_SOFT_DECLARATIONS3 353 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 354 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 355 #define I2C_SOFT_DECLARATIONS4 356 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 357 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 358 #define I2C_SOFT_DECLARATIONS5 359 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 360 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 361 #define I2C_SOFT_DECLARATIONS6 362 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 364 #define I2C_SOFT_DECLARATIONS7 365 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 367 #define I2C_SOFT_DECLARATIONS8 368 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 370 371 #ifdef CONFIG_HRCON_DH 372 #define I2C_SOFT_DECLARATIONS9 373 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 374 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 375 #define I2C_SOFT_DECLARATIONS10 376 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 378 #define I2C_SOFT_DECLARATIONS11 379 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 380 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 381 #define I2C_SOFT_DECLARATIONS12 382 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 383 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 384 #endif 385 386 #ifdef CONFIG_HRCON_DH 387 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 388 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 389 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ 390 {12, 0x4c} } 391 #else 392 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} 393 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 394 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ 395 {8, 0x4c} } 396 #endif 397 398 #ifndef __ASSEMBLY__ 399 void fpga_gpio_set(unsigned int bus, int pin); 400 void fpga_gpio_clear(unsigned int bus, int pin); 401 int fpga_gpio_get(unsigned int bus, int pin); 402 void fpga_control_set(unsigned int bus, int pin); 403 void fpga_control_clear(unsigned int bus, int pin); 404 #endif 405 406 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 407 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 408 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 409 410 #ifdef CONFIG_HRCON_DH 411 #define I2C_ACTIVE \ 412 do { \ 413 if (I2C_ADAP_HWNR > 7) \ 414 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 415 else \ 416 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 417 } while (0) 418 #else 419 #define I2C_ACTIVE { } 420 #endif 421 #define I2C_TRISTATE { } 422 #define I2C_READ \ 423 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 424 #define I2C_SDA(bit) \ 425 do { \ 426 if (bit) \ 427 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 428 else \ 429 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 430 } while (0) 431 #define I2C_SCL(bit) \ 432 do { \ 433 if (bit) \ 434 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 435 else \ 436 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 437 } while (0) 438 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 439 440 /* 441 * Software (bit-bang) MII driver configuration 442 */ 443 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 444 #define CONFIG_BITBANGMII_MULTI 445 446 /* 447 * OSD Setup 448 */ 449 #define CONFIG_SYS_OSD_SCREENS 1 450 #define CONFIG_SYS_DP501_DIFFERENTIAL 451 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 452 453 #ifdef CONFIG_HRCON_DH 454 #define CONFIG_SYS_OSD_DH 455 #endif 456 457 /* 458 * General PCI 459 * Addresses are mapped 1-1. 460 */ 461 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 462 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 463 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 464 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 465 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 466 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 467 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 468 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 469 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 470 471 /* enable PCIE clock */ 472 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 473 474 #define CONFIG_PCI_INDIRECT_BRIDGE 475 #define CONFIG_PCIE 476 477 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 478 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 479 480 /* 481 * TSEC 482 */ 483 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 484 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 485 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 486 487 /* 488 * TSEC ethernet configuration 489 */ 490 #define CONFIG_MII 1 /* MII PHY management */ 491 #define CONFIG_TSEC1 492 #define CONFIG_TSEC1_NAME "eTSEC0" 493 #define TSEC1_PHY_ADDR 1 494 #define TSEC1_PHYIDX 0 495 #define TSEC1_FLAGS TSEC_GIGABIT 496 497 /* Options are: eTSEC[0-1] */ 498 #define CONFIG_ETHPRIME "eTSEC0" 499 500 /* 501 * Environment 502 */ 503 #if 1 504 #define CONFIG_ENV_IS_IN_FLASH 1 505 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 506 CONFIG_SYS_MONITOR_LEN) 507 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 508 #define CONFIG_ENV_SIZE 0x2000 509 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 510 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 511 #else 512 #define CONFIG_ENV_IS_NOWHERE 513 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 514 #endif 515 516 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 517 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 518 519 /* 520 * Command line configuration. 521 */ 522 #define CONFIG_CMD_PCI 523 524 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 525 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 526 527 /* 528 * Miscellaneous configurable options 529 */ 530 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 531 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 532 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 533 534 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 535 536 /* Print Buffer Size */ 537 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 538 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 539 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 540 541 /* 542 * For booting Linux, the board info and command line data 543 * have to be in the first 256 MB of memory, since this is 544 * the maximum mapped by the Linux kernel during initialization. 545 */ 546 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 547 548 /* 549 * Core HID Setup 550 */ 551 #define CONFIG_SYS_HID0_INIT 0x000000000 552 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 553 HID0_ENABLE_INSTRUCTION_CACHE | \ 554 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 555 #define CONFIG_SYS_HID2 HID2_HBE 556 557 /* 558 * MMU Setup 559 */ 560 561 /* DDR: cache cacheable */ 562 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 563 BATL_MEMCOHERENCE) 564 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 565 BATU_VS | BATU_VP) 566 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 567 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 568 569 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 570 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 571 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 572 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 573 BATU_VP) 574 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 575 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 576 577 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 578 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 579 BATL_MEMCOHERENCE) 580 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 581 BATU_VS | BATU_VP) 582 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 583 BATL_CACHEINHIBIT | \ 584 BATL_GUARDEDSTORAGE) 585 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 586 587 /* Stack in dcache: cacheable, no memory coherence */ 588 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 589 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 590 BATU_VS | BATU_VP) 591 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 592 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 593 594 /* 595 * Environment Configuration 596 */ 597 598 #define CONFIG_ENV_OVERWRITE 599 600 #if defined(CONFIG_TSEC_ENET) 601 #define CONFIG_HAS_ETH0 602 #endif 603 604 #define CONFIG_BAUDRATE 115200 605 606 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 607 608 609 #define CONFIG_HOSTNAME hrcon 610 #define CONFIG_ROOTPATH "/opt/nfsroot" 611 #define CONFIG_BOOTFILE "uImage" 612 613 #define CONFIG_PREBOOT /* enable preboot variable */ 614 615 #define CONFIG_EXTRA_ENV_SETTINGS \ 616 "netdev=eth0\0" \ 617 "consoledev=ttyS1\0" \ 618 "u-boot=u-boot.bin\0" \ 619 "kernel_addr=1000000\0" \ 620 "fdt_addr=C00000\0" \ 621 "fdtfile=hrcon.dtb\0" \ 622 "load=tftp ${loadaddr} ${u-boot}\0" \ 623 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 624 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 625 " +${filesize};cp.b ${fileaddr} " \ 626 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 627 "upd=run load update\0" \ 628 629 #define CONFIG_NFSBOOTCOMMAND \ 630 "setenv bootargs root=/dev/nfs rw " \ 631 "nfsroot=$serverip:$rootpath " \ 632 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 633 "console=$consoledev,$baudrate $othbootargs;" \ 634 "tftp ${kernel_addr} $bootfile;" \ 635 "tftp ${fdt_addr} $fdtfile;" \ 636 "bootm ${kernel_addr} - ${fdt_addr}" 637 638 #define CONFIG_MMCBOOTCOMMAND \ 639 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 640 "console=$consoledev,$baudrate $othbootargs;" \ 641 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 642 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 643 "bootm ${kernel_addr} - ${fdt_addr}" 644 645 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 646 647 #endif /* __CONFIG_H */ 648