xref: /openbmc/u-boot/include/configs/highbank.h (revision aa5e3e22)
1 /*
2  * Copyright 2010-2011 Calxeda, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9 
10 #define CONFIG_SYS_DCACHE_OFF
11 
12 #define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
13 
14 #define CONFIG_SYS_TIMER_RATE		(150000000/256)
15 #define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
16 #define CONFIG_SYS_TIMER_COUNTS_DOWN
17 
18 /*
19  * Size of malloc() pool
20  */
21 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
22 
23 #define CONFIG_PL011_CLOCK		150000000
24 #define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
25 #define CONFIG_CONS_INDEX		0
26 
27 #define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
28 
29 #define CONFIG_MISC_INIT_R
30 #define CONFIG_SCSI_AHCI_PLAT
31 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
32 #define CONFIG_SYS_SCSI_MAX_LUN		1
33 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
34 					CONFIG_SYS_SCSI_MAX_LUN)
35 
36 #define CONFIG_CALXEDA_XGMAC
37 
38 /*
39  * Command line configuration.
40  */
41 
42 #define CONFIG_BOOT_RETRY_TIME		-1
43 #define CONFIG_RESET_TO_RETRY
44 
45 /*
46  * Miscellaneous configurable options
47  */
48 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
49 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
50 
51 #define CONFIG_SYS_LOAD_ADDR		0x800000
52 #define CONFIG_SYS_64BIT_LBA
53 
54 /*-----------------------------------------------------------------------
55  * Physical Memory Map
56  * The DRAM is already setup, so do not touch the DT node later.
57  */
58 #define CONFIG_NR_DRAM_BANKS		0
59 #define PHYS_SDRAM_1_SIZE		(4089 << 20)
60 #define CONFIG_SYS_MEMTEST_START	0x100000
61 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1_SIZE - 0x100000)
62 
63 /* Environment data setup
64 */
65 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
66 #define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
67 #define CONFIG_ENV_SIZE			0x2000		/* Size of Environ */
68 #define CONFIG_ENV_ADDR			CONFIG_SYS_NVRAM_BASE_ADDR
69 
70 #define CONFIG_SYS_SDRAM_BASE		0x00000000
71 #define CONFIG_SYS_INIT_SP_ADDR		0x01000000
72 #define CONFIG_SKIP_LOWLEVEL_INIT
73 
74 #endif
75