xref: /openbmc/u-boot/include/configs/highbank.h (revision 12308b12)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2010-2011 Calxeda, Inc.
4  */
5 
6 #ifndef __CONFIG_H
7 #define __CONFIG_H
8 
9 #define CONFIG_SYS_DCACHE_OFF
10 
11 #define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
12 
13 #define CONFIG_SYS_TIMER_RATE		(150000000/256)
14 #define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
15 #define CONFIG_SYS_TIMER_COUNTS_DOWN
16 
17 /*
18  * Size of malloc() pool
19  */
20 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
21 
22 #define CONFIG_PL011_CLOCK		150000000
23 #define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
24 
25 #define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
26 
27 #define CONFIG_MISC_INIT_R
28 #define CONFIG_SCSI_AHCI_PLAT
29 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
30 #define CONFIG_SYS_SCSI_MAX_LUN		1
31 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
32 					CONFIG_SYS_SCSI_MAX_LUN)
33 
34 #define CONFIG_CALXEDA_XGMAC
35 
36 /*
37  * Command line configuration.
38  */
39 
40 #define CONFIG_BOOT_RETRY_TIME		-1
41 #define CONFIG_RESET_TO_RETRY
42 
43 /*
44  * Miscellaneous configurable options
45  */
46 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
47 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
48 
49 #define CONFIG_SYS_LOAD_ADDR		0x800000
50 #define CONFIG_SYS_64BIT_LBA
51 
52 /*-----------------------------------------------------------------------
53  * Physical Memory Map
54  * The DRAM is already setup, so do not touch the DT node later.
55  */
56 #define CONFIG_NR_DRAM_BANKS		0
57 #define PHYS_SDRAM_1_SIZE		(4089 << 20)
58 #define CONFIG_SYS_MEMTEST_START	0x100000
59 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1_SIZE - 0x100000)
60 
61 /* Environment data setup
62 */
63 #define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
64 #define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
65 #define CONFIG_ENV_SIZE			0x2000		/* Size of Environ */
66 #define CONFIG_ENV_ADDR			CONFIG_SYS_NVRAM_BASE_ADDR
67 
68 #define CONFIG_SYS_SDRAM_BASE		0x00000000
69 #define CONFIG_SYS_INIT_SP_ADDR		0x01000000
70 #define CONFIG_SKIP_LOWLEVEL_INIT
71 
72 #endif
73