1 /* 2 * iPAQ h2200 board configuration 3 * 4 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_MACH_TYPE MACH_TYPE_H2200 13 14 #define CONFIG_CPU_PXA25X 1 15 16 #define CONFIG_NR_DRAM_BANKS 1 17 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 18 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 19 20 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 21 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE 22 23 #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 24 25 #define CONFIG_ENV_SIZE 0x00040000 26 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 27 28 #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ 29 30 /* 31 * iPAQ 1st stage bootloader loads 2nd stage bootloader 32 * at address 0xa0040000 but bootloader requires header 33 * which is 0x1000 long. 34 * 35 * --- Header begin --- 36 * .word 0xea0003fe ; b 0x1000 37 * 38 * .org 0x40 39 * .ascii "ECEC" 40 * 41 * .org 0x1000 42 * --- Header end --- 43 */ 44 45 /* 46 * Static chips 47 */ 48 49 #define CONFIG_SYS_MSC0_VAL 0x246c7ffc 50 #define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 51 #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 52 53 /* 54 * PCMCIA and CF Interfaces 55 */ 56 57 #define CONFIG_SYS_MECR_VAL 0x00000000 58 #define CONFIG_SYS_MCMEM0_VAL 0x00000000 59 #define CONFIG_SYS_MCMEM1_VAL 0x00000000 60 #define CONFIG_SYS_MCATT0_VAL 0x00000000 61 #define CONFIG_SYS_MCATT1_VAL 0x00000000 62 #define CONFIG_SYS_MCIO0_VAL 0x00000000 63 #define CONFIG_SYS_MCIO1_VAL 0x00000000 64 65 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 66 #define CONFIG_SYS_SXCNFG_VAL 0x00040004 67 68 #define CONFIG_SYS_MDREFR_VAL 0x0099E018 69 #define CONFIG_SYS_MDCNFG_VAL 0x01C801CB 70 #define CONFIG_SYS_MDMRS_VAL 0x00220022 71 72 #define CONFIG_SYS_PSSR_VAL 0x00000000 73 #define CONFIG_SYS_CKEN 0x00004840 74 #define CONFIG_SYS_CCCR 0x00000161 75 76 /* 77 * GPIOs 78 */ 79 80 #define CONFIG_SYS_GPSR0_VAL 0x01000000 81 #define CONFIG_SYS_GPSR1_VAL 0x00000000 82 #define CONFIG_SYS_GPSR2_VAL 0x00010000 83 84 #define CONFIG_SYS_GPCR0_VAL 0x00000000 85 #define CONFIG_SYS_GPCR1_VAL 0x00000000 86 #define CONFIG_SYS_GPCR2_VAL 0x00000000 87 88 #define CONFIG_SYS_GPDR0_VAL 0xF7E38C00 89 #define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83 90 #define CONFIG_SYS_GPDR2_VAL 0x000157FF 91 92 #define CONFIG_SYS_GAFR0_L_VAL 0x80401000 93 #define CONFIG_SYS_GAFR0_U_VAL 0x00000112 94 #define CONFIG_SYS_GAFR1_L_VAL 0x600A9550 95 #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 96 #define CONFIG_SYS_GAFR2_L_VAL 0x20000000 97 #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 98 99 /* 100 * Serial port 101 */ 102 #define CONFIG_FFUART 103 104 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } 105 106 #define CONFIG_SETUP_MEMORY_TAGS 107 #define CONFIG_CMDLINE_TAG 108 #define CONFIG_INITRD_TAG 109 110 /* Monitor Command Prompt */ 111 112 #define CONFIG_USB_DEV_PULLUP_GPIO 33 113 /* USB VBUS GPIO 3 */ 114 115 #define CONFIG_BOOTCOMMAND \ 116 "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \ 117 "if bootp ; then setenv downloaded 1 ; fi ; done ; " \ 118 "source :script ; " \ 119 "bootm ; " 120 121 #define CONFIG_USB_GADGET_PXA2XX 122 #define CONFIG_USB_ETH_SUBSET 123 124 #define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01" 125 #define CONFIG_EXTRA_ENV_SETTINGS \ 126 "stdin=serial\0" \ 127 "stdout=serial\0" \ 128 "stderr=serial\0" 129 130 #endif /* __CONFIG_H */ 131