1 /* 2 * iPAQ h2200 board configuration 3 * 4 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_MACH_TYPE MACH_TYPE_H2200 13 14 #define CONFIG_CPU_PXA25X 1 15 #define CONFIG_BOARD_H2200 16 17 #define CONFIG_SYS_NO_FLASH 18 19 #define CONFIG_NR_DRAM_BANKS 1 20 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 21 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 22 23 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 24 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE 25 26 #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 27 28 #define CONFIG_ENV_SIZE 0x00040000 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 30 31 #define CONFIG_ENV_IS_NOWHERE 32 #define CONFIG_SYS_MAXARGS 16 33 #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ 34 35 /* 36 * iPAQ 1st stage bootloader loads 2nd stage bootloader 37 * at address 0xa0040000 but bootloader requires header 38 * which is 0x1000 long. 39 * 40 * --- Header begin --- 41 * .word 0xea0003fe ; b 0x1000 42 * 43 * .org 0x40 44 * .ascii "ECEC" 45 * 46 * .org 0x1000 47 * --- Header end --- 48 */ 49 50 #define CONFIG_SYS_TEXT_BASE 0xa0041000 51 52 /* 53 * Static chips 54 */ 55 56 #define CONFIG_SYS_MSC0_VAL 0x246c7ffc 57 #define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 58 #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 59 60 /* 61 * PCMCIA and CF Interfaces 62 */ 63 64 #define CONFIG_SYS_MECR_VAL 0x00000000 65 #define CONFIG_SYS_MCMEM0_VAL 0x00000000 66 #define CONFIG_SYS_MCMEM1_VAL 0x00000000 67 #define CONFIG_SYS_MCATT0_VAL 0x00000000 68 #define CONFIG_SYS_MCATT1_VAL 0x00000000 69 #define CONFIG_SYS_MCIO0_VAL 0x00000000 70 #define CONFIG_SYS_MCIO1_VAL 0x00000000 71 72 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 73 #define CONFIG_SYS_SXCNFG_VAL 0x00040004 74 75 #define CONFIG_SYS_MDREFR_VAL 0x0099E018 76 #define CONFIG_SYS_MDCNFG_VAL 0x01C801CB 77 #define CONFIG_SYS_MDMRS_VAL 0x00220022 78 79 #define CONFIG_SYS_PSSR_VAL 0x00000000 80 #define CONFIG_SYS_CKEN 0x00004840 81 #define CONFIG_SYS_CCCR 0x00000161 82 83 /* 84 * GPIOs 85 */ 86 87 #define CONFIG_SYS_GPSR0_VAL 0x01000000 88 #define CONFIG_SYS_GPSR1_VAL 0x00000000 89 #define CONFIG_SYS_GPSR2_VAL 0x00010000 90 91 #define CONFIG_SYS_GPCR0_VAL 0x00000000 92 #define CONFIG_SYS_GPCR1_VAL 0x00000000 93 #define CONFIG_SYS_GPCR2_VAL 0x00000000 94 95 #define CONFIG_SYS_GPDR0_VAL 0xF7E38C00 96 #define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83 97 #define CONFIG_SYS_GPDR2_VAL 0x000157FF 98 99 #define CONFIG_SYS_GAFR0_L_VAL 0x80401000 100 #define CONFIG_SYS_GAFR0_U_VAL 0x00000112 101 #define CONFIG_SYS_GAFR1_L_VAL 0x600A9550 102 #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 103 #define CONFIG_SYS_GAFR2_L_VAL 0x20000000 104 #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 105 106 /* 107 * Serial port 108 */ 109 #define CONFIG_FFUART 110 #define CONFIG_CONS_INDEX 3 111 112 #define CONFIG_BAUDRATE 115200 113 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } 114 115 #define CONFIG_FIT_DISABLE_SHA256 116 #define CONFIG_SETUP_MEMORY_TAGS 117 #define CONFIG_CMDLINE_TAG 118 #define CONFIG_INITRD_TAG 119 120 /* Monitor Command Prompt */ 121 122 /* Console I/O Buffer Size */ 123 #define CONFIG_SYS_CBSIZE 256 124 125 /* Print Buffer Size */ 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 127 sizeof(CONFIG_SYS_PROMPT) + 16) 128 129 #define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8" 130 131 #define CONFIG_USB_DEV_PULLUP_GPIO 33 132 /* USB VBUS GPIO 3 */ 133 134 #define CONFIG_BOOTCOMMAND \ 135 "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \ 136 "if bootp ; then setenv downloaded 1 ; fi ; done ; " \ 137 "source :script ; " \ 138 "bootm ; " 139 140 #define CONFIG_USB_GADGET_PXA2XX 141 #define CONFIG_USB_ETHER 142 #define CONFIG_USB_ETH_SUBSET 143 144 #define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01" 145 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef:00:02" 146 #define CONFIG_EXTRA_ENV_SETTINGS \ 147 "stdin=serial\0" \ 148 "stdout=serial\0" \ 149 "stderr=serial\0" 150 151 #endif /* __CONFIG_H */ 152