1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * iPAQ h2200 board configuration 4 * 5 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #define CONFIG_MACH_TYPE MACH_TYPE_H2200 12 13 #define CONFIG_CPU_PXA25X 1 14 15 #define CONFIG_NR_DRAM_BANKS 1 16 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 17 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 18 19 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 20 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE 21 22 #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 23 24 #define CONFIG_ENV_SIZE 0x00040000 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 26 27 #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ 28 29 /* 30 * iPAQ 1st stage bootloader loads 2nd stage bootloader 31 * at address 0xa0040000 but bootloader requires header 32 * which is 0x1000 long. 33 * 34 * --- Header begin --- 35 * .word 0xea0003fe ; b 0x1000 36 * 37 * .org 0x40 38 * .ascii "ECEC" 39 * 40 * .org 0x1000 41 * --- Header end --- 42 */ 43 44 /* 45 * Static chips 46 */ 47 48 #define CONFIG_SYS_MSC0_VAL 0x246c7ffc 49 #define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 50 #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 51 52 /* 53 * PCMCIA and CF Interfaces 54 */ 55 56 #define CONFIG_SYS_MECR_VAL 0x00000000 57 #define CONFIG_SYS_MCMEM0_VAL 0x00000000 58 #define CONFIG_SYS_MCMEM1_VAL 0x00000000 59 #define CONFIG_SYS_MCATT0_VAL 0x00000000 60 #define CONFIG_SYS_MCATT1_VAL 0x00000000 61 #define CONFIG_SYS_MCIO0_VAL 0x00000000 62 #define CONFIG_SYS_MCIO1_VAL 0x00000000 63 64 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 65 #define CONFIG_SYS_SXCNFG_VAL 0x00040004 66 67 #define CONFIG_SYS_MDREFR_VAL 0x0099E018 68 #define CONFIG_SYS_MDCNFG_VAL 0x01C801CB 69 #define CONFIG_SYS_MDMRS_VAL 0x00220022 70 71 #define CONFIG_SYS_PSSR_VAL 0x00000000 72 #define CONFIG_SYS_CKEN 0x00004840 73 #define CONFIG_SYS_CCCR 0x00000161 74 75 /* 76 * GPIOs 77 */ 78 79 #define CONFIG_SYS_GPSR0_VAL 0x01000000 80 #define CONFIG_SYS_GPSR1_VAL 0x00000000 81 #define CONFIG_SYS_GPSR2_VAL 0x00010000 82 83 #define CONFIG_SYS_GPCR0_VAL 0x00000000 84 #define CONFIG_SYS_GPCR1_VAL 0x00000000 85 #define CONFIG_SYS_GPCR2_VAL 0x00000000 86 87 #define CONFIG_SYS_GPDR0_VAL 0xF7E38C00 88 #define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83 89 #define CONFIG_SYS_GPDR2_VAL 0x000157FF 90 91 #define CONFIG_SYS_GAFR0_L_VAL 0x80401000 92 #define CONFIG_SYS_GAFR0_U_VAL 0x00000112 93 #define CONFIG_SYS_GAFR1_L_VAL 0x600A9550 94 #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 95 #define CONFIG_SYS_GAFR2_L_VAL 0x20000000 96 #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 97 98 /* 99 * Serial port 100 */ 101 #define CONFIG_FFUART 102 103 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } 104 105 #define CONFIG_SETUP_MEMORY_TAGS 106 #define CONFIG_CMDLINE_TAG 107 #define CONFIG_INITRD_TAG 108 109 /* Monitor Command Prompt */ 110 111 #define CONFIG_USB_DEV_PULLUP_GPIO 33 112 /* USB VBUS GPIO 3 */ 113 114 #define CONFIG_BOOTCOMMAND \ 115 "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \ 116 "if bootp ; then setenv downloaded 1 ; fi ; done ; " \ 117 "source :script ; " \ 118 "bootm ; " 119 120 #define CONFIG_USB_GADGET_PXA2XX 121 #define CONFIG_USB_ETH_SUBSET 122 123 #define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01" 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "stdin=serial\0" \ 126 "stdout=serial\0" \ 127 "stderr=serial\0" 128 129 #endif /* __CONFIG_H */ 130