1 /* 2 * Copyright (C) 2013 Gateworks Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* SPL */ 11 /* Location in NAND to read U-Boot from */ 12 #define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M) 13 14 /* Falcon Mode */ 15 #define CONFIG_CMD_SPL 16 #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 17 #define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) 18 19 /* Falcon Mode - NAND support: args@17MB kernel@18MB */ 20 #define CONFIG_CMD_SPL_NAND_OFS (17 * SZ_1M) 21 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M) 22 23 /* Falcon Mode - MMC support: args@1MB kernel@2MB */ 24 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ 25 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) 26 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ 27 28 #include "imx6_spl.h" /* common IMX6 SPL configuration */ 29 #include "mx6_common.h" 30 #define CONFIG_DISPLAY_BOARDINFO_LATE 31 32 #define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ 33 34 /* Serial ATAG */ 35 #define CONFIG_SERIAL_TAG 36 37 /* Size of malloc() pool */ 38 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) 39 40 /* Init Functions */ 41 #define CONFIG_MISC_INIT_R 42 43 /* Driver Model */ 44 #ifndef CONFIG_SPL_BUILD 45 #define CONFIG_DM_GPIO 46 #define CONFIG_DM_THERMAL 47 #endif 48 49 /* Thermal */ 50 #define CONFIG_IMX_THERMAL 51 52 /* Serial */ 53 #define CONFIG_MXC_UART 54 #define CONFIG_MXC_UART_BASE UART2_BASE 55 56 #ifdef CONFIG_SPI_FLASH 57 58 /* SPI */ 59 #ifdef CONFIG_CMD_SF 60 #define CONFIG_MXC_SPI 61 #define CONFIG_SPI_FLASH_MTD 62 #define CONFIG_SPI_FLASH_BAR 63 #define CONFIG_SF_DEFAULT_BUS 0 64 #define CONFIG_SF_DEFAULT_CS 0 65 /* GPIO 3-19 (21248) */ 66 #define CONFIG_SF_DEFAULT_SPEED 30000000 67 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 68 #endif 69 70 #elif defined(CONFIG_SPL_NAND_SUPPORT) 71 /* Enable NAND support */ 72 #ifdef CONFIG_CMD_NAND 73 #define CONFIG_NAND_MXS 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 75 #define CONFIG_SYS_NAND_BASE 0x40000000 76 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 77 #define CONFIG_SYS_NAND_ONFI_DETECTION 78 79 /* DMA stuff, needed for GPMI/MXS NAND support */ 80 #define CONFIG_APBH_DMA 81 #define CONFIG_APBH_DMA_BURST 82 #define CONFIG_APBH_DMA_BURST8 83 #endif 84 85 #endif /* CONFIG_SPI_FLASH */ 86 87 /* I2C Configs */ 88 #define CONFIG_SYS_I2C 89 #define CONFIG_SYS_I2C_MXC 90 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 91 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 92 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 93 #define CONFIG_SYS_I2C_SPEED 100000 94 #define CONFIG_I2C_GSC 0 95 #define CONFIG_I2C_EDID 96 97 /* MMC Configs */ 98 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 99 100 /* eMMC Configs */ 101 #define CONFIG_SUPPORT_EMMC_BOOT 102 #define CONFIG_SUPPORT_EMMC_RPMB 103 104 /* 105 * SATA Configs 106 */ 107 #ifdef CONFIG_CMD_SATA 108 #define CONFIG_DWC_AHSATA 109 #define CONFIG_SYS_SATA_MAX_DEVICE 1 110 #define CONFIG_DWC_AHSATA_PORT_ID 0 111 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 112 #define CONFIG_LBA48 113 #define CONFIG_LIBATA 114 #endif 115 116 /* 117 * PCI express 118 */ 119 #define CONFIG_CMD_PCI 120 #ifdef CONFIG_CMD_PCI 121 #define CONFIG_PCI_SCAN_SHOW 122 #define CONFIG_PCI_FIXUP_DEV 123 #define CONFIG_PCIE_IMX 124 #endif 125 126 /* 127 * PMIC 128 */ 129 #define CONFIG_POWER 130 #define CONFIG_POWER_I2C 131 #define CONFIG_POWER_PFUZE100 132 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 133 #define CONFIG_POWER_LTC3676 134 #define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c 135 136 /* Various command support */ 137 #define CONFIG_CMD_UNZIP /* gzwrite */ 138 139 /* Ethernet support */ 140 #define CONFIG_FEC_MXC 141 #define CONFIG_MII 142 #define IMX_FEC_BASE ENET_BASE_ADDR 143 #define CONFIG_FEC_XCV_TYPE RGMII 144 #define CONFIG_FEC_MXC_PHYADDR 0 145 #define CONFIG_ARP_TIMEOUT 200UL 146 147 /* USB Configs */ 148 #define CONFIG_USB_HOST_ETHER 149 #define CONFIG_USB_ETHER_ASIX 150 #define CONFIG_USB_ETHER_SMSC95XX 151 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 152 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 153 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 154 #define CONFIG_MXC_USB_FLAGS 0 155 #define CONFIG_USBD_HS 156 #define CONFIG_USB_ETHER 157 #define CONFIG_USB_ETH_CDC 158 #define CONFIG_NETCONSOLE 159 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP 160 161 /* USB Mass Storage Gadget */ 162 #define CONFIG_USB_FUNCTION_MASS_STORAGE 163 164 /* Framebuffer and LCD */ 165 #define CONFIG_VIDEO_IPUV3 166 #define CONFIG_VIDEO_LOGO 167 #define CONFIG_IPUV3_CLK 260000000 168 #define CONFIG_IMX_HDMI 169 #define CONFIG_IMX_VIDEO_SKIP 170 #define CONFIG_VIDEO_BMP_LOGO 171 #define CONFIG_SPLASH_SCREEN_ALIGN 172 #define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */ 173 174 /* Miscellaneous configurable options */ 175 #define CONFIG_HWCONFIG 176 #define CONFIG_PREBOOT 177 178 /* Print Buffer Size */ 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 180 181 /* Memory configuration */ 182 #define CONFIG_SYS_MEMTEST_START 0x10000000 183 #define CONFIG_SYS_MEMTEST_END 0x10010000 184 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 185 186 /* Physical Memory Map */ 187 #define CONFIG_NR_DRAM_BANKS 1 188 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 189 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 190 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 191 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 192 193 #define CONFIG_SYS_INIT_SP_OFFSET \ 194 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 195 #define CONFIG_SYS_INIT_SP_ADDR \ 196 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 197 198 /* 199 * MTD Command for mtdparts 200 */ 201 #define CONFIG_MTD_DEVICE 202 #define CONFIG_MTD_PARTITIONS 203 #ifdef CONFIG_SPI_FLASH 204 #define MTDIDS_DEFAULT "nor0=nor" 205 #define MTDPARTS_DEFAULT \ 206 "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" 207 #else 208 #define MTDIDS_DEFAULT "nand0=nand" 209 #define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" 210 #endif 211 212 /* Persistent Environment Config */ 213 #if defined(CONFIG_ENV_IS_IN_MMC) 214 #define CONFIG_SYS_MMC_ENV_DEV 0 215 #define CONFIG_SYS_MMC_ENV_PART 1 216 #define CONFIG_ENV_OFFSET (709 * SZ_1K) 217 #define CONFIG_ENV_SIZE (128 * SZ_1K) 218 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K)) 219 #elif defined(CONFIG_ENV_IS_IN_NAND) 220 #define CONFIG_ENV_OFFSET (16 * SZ_1M) 221 #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) 222 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 223 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 * SZ_1K)) 224 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 225 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) 226 #define CONFIG_ENV_OFFSET (512 * SZ_1K) 227 #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) 228 #define CONFIG_ENV_SIZE (8 * SZ_1K) 229 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 230 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 231 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 232 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 233 #endif 234 235 /* Environment */ 236 #define CONFIG_IPADDR 192.168.1.1 237 #define CONFIG_SERVERIP 192.168.1.146 238 239 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ 240 "pcidisable=1\0" \ 241 "splashpos=m,m\0" \ 242 "usb_pgood_delay=2000\0" \ 243 "console=ttymxc1\0" \ 244 "bootdevs=usb mmc sata flash\0" \ 245 "hwconfig=_UNKNOWN_\0" \ 246 "video=\0" \ 247 \ 248 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 249 "mtdids=" MTDIDS_DEFAULT "\0" \ 250 "disk=0\0" \ 251 "part=1\0" \ 252 \ 253 "fdt_high=0xffffffff\0" \ 254 "fdt_addr=0x18000000\0" \ 255 "initrd_high=0xffffffff\0" \ 256 "fixfdt=" \ 257 "fdt addr ${fdt_addr}\0" \ 258 "bootdir=boot\0" \ 259 "loadfdt=" \ 260 "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ 261 "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ 262 "run fixfdt; " \ 263 "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ 264 "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ 265 "run fixfdt; " \ 266 "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ 267 "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ 268 "run fixfdt; " \ 269 "fi\0" \ 270 \ 271 "fs=ext4\0" \ 272 "script=6x_bootscript-ventana\0" \ 273 "loadscript=" \ 274 "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ 275 "source ${loadaddr}; " \ 276 "fi\0" \ 277 \ 278 "uimage=uImage\0" \ 279 "mmc_root=mmcblk0p1\0" \ 280 "mmc_boot=" \ 281 "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ 282 "mmc dev ${disk} && mmc rescan && " \ 283 "setenv dtype mmc; run loadscript; " \ 284 "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ 285 "setenv bootargs console=${console},${baudrate} " \ 286 "root=/dev/${mmc_root} rootfstype=${fs} " \ 287 "rootwait rw ${video} ${extra}; " \ 288 "if run loadfdt; then " \ 289 "bootm ${loadaddr} - ${fdt_addr}; " \ 290 "else " \ 291 "bootm; " \ 292 "fi; " \ 293 "fi\0" \ 294 \ 295 "sata_boot=" \ 296 "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \ 297 "sata init && " \ 298 "setenv dtype sata; run loadscript; " \ 299 "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ 300 "setenv bootargs console=${console},${baudrate} " \ 301 "root=/dev/sda1 rootfstype=${fs} " \ 302 "rootwait rw ${video} ${extra}; " \ 303 "if run loadfdt; then " \ 304 "bootm ${loadaddr} - ${fdt_addr}; " \ 305 "else " \ 306 "bootm; " \ 307 "fi; " \ 308 "fi\0" \ 309 "usb_boot=" \ 310 "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \ 311 "usb start && usb dev ${disk} && " \ 312 "setenv dtype usb; run loadscript; " \ 313 "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ 314 "setenv bootargs console=${console},${baudrate} " \ 315 "root=/dev/sda1 rootfstype=${fs} " \ 316 "rootwait rw ${video} ${extra}; " \ 317 "if run loadfdt; then " \ 318 "bootm ${loadaddr} - ${fdt_addr}; " \ 319 "else " \ 320 "bootm; " \ 321 "fi; " \ 322 "fi\0" 323 324 #ifdef CONFIG_SPI_FLASH 325 #define CONFIG_EXTRA_ENV_SETTINGS \ 326 CONFIG_EXTRA_ENV_SETTINGS_COMMON \ 327 "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ 328 "image_uboot=ventana/u-boot_spi.imx\0" \ 329 \ 330 "spi_koffset=0x90000\0" \ 331 "spi_klen=0x200000\0" \ 332 \ 333 "spi_updateuboot=echo Updating uboot from " \ 334 "${serverip}:${image_uboot}...; " \ 335 "tftpboot ${loadaddr} ${image_uboot} && " \ 336 "sf probe && sf erase 0 80000 && " \ 337 "sf write ${loadaddr} 400 ${filesize}\0" \ 338 "spi_update=echo Updating OS from ${serverip}:${image_os} " \ 339 "to ${spi_koffset} ...; " \ 340 "tftp ${loadaddr} ${image_os} && " \ 341 "sf probe && " \ 342 "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ 343 \ 344 "flash_boot=" \ 345 "if sf probe && " \ 346 "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ 347 "setenv bootargs console=${console},${baudrate} " \ 348 "root=/dev/mtdblock3 " \ 349 "rootfstype=squashfs,jffs2 " \ 350 "${video} ${extra}; " \ 351 "bootm; " \ 352 "fi\0" 353 #else 354 #define CONFIG_EXTRA_ENV_SETTINGS \ 355 CONFIG_EXTRA_ENV_SETTINGS_COMMON \ 356 \ 357 "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ 358 "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ 359 "tftp ${loadaddr} ${image_rootfs} && " \ 360 "nand erase.part rootfs && " \ 361 "nand write ${loadaddr} rootfs ${filesize}\0" \ 362 \ 363 "flash_boot=" \ 364 "setenv fsload 'ubifsload'; " \ 365 "ubi part rootfs; " \ 366 "if ubi check boot; then " \ 367 "ubifsmount ubi0:boot; " \ 368 "setenv root ubi0:rootfs ubi.mtd=2 " \ 369 "rootfstype=squashfs,ubifs; " \ 370 "setenv bootdir; " \ 371 "elif ubi check rootfs; then " \ 372 "ubifsmount ubi0:rootfs; " \ 373 "setenv root ubi0:rootfs ubi.mtd=2 " \ 374 "rootfstype=ubifs; " \ 375 "fi; " \ 376 "setenv dtype nand; run loadscript; " \ 377 "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ 378 "setenv bootargs console=${console},${baudrate} " \ 379 "root=${root} ${video} ${extra}; " \ 380 "if run loadfdt; then " \ 381 "ubifsumount; " \ 382 "bootm ${loadaddr} - ${fdt_addr}; " \ 383 "else " \ 384 "ubifsumount; bootm; " \ 385 "fi; " \ 386 "fi\0" 387 #endif 388 389 #define CONFIG_BOOTCOMMAND \ 390 "for btype in ${bootdevs}; do " \ 391 "echo; echo Attempting ${btype} boot...; " \ 392 "if run ${btype}_boot; then; fi; " \ 393 "done" 394 395 #endif /* __CONFIG_H */ 396