1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * include/configs/gose.h 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 */ 7 8 #ifndef __GOSE_H 9 #define __GOSE_H 10 11 #include "rcar-gen2-common.h" 12 13 #define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 14 #define STACK_AREA_SIZE 0x00100000 15 #define LOW_LEVEL_MERAM_STACK \ 16 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 17 18 /* MEMORY */ 19 #define RCAR_GEN2_SDRAM_BASE 0x40000000 20 #define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) 21 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) 22 23 /* SH Ether */ 24 #define CONFIG_SH_ETHER_USE_PORT 0 25 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 26 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 27 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 28 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 29 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 30 #define CONFIG_BITBANGMII 31 #define CONFIG_BITBANGMII_MULTI 32 33 /* Board Clock */ 34 #define RMOBILE_XTAL_CLK 20000000u 35 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 36 37 #define CONFIG_EXTRA_ENV_SETTINGS \ 38 "fdt_high=0xffffffff\0" \ 39 "initrd_high=0xffffffff\0" 40 41 /* SPL support */ 42 #define CONFIG_SPL_TEXT_BASE 0xe6300000 43 #define CONFIG_SPL_STACK 0xe6340000 44 #define CONFIG_SPL_MAX_SIZE 0x4000 45 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_CONS_SCIF0 48 #define CONFIG_SH_SCIF_CLK_FREQ 65000000 49 #endif 50 51 #endif /* __GOSE_H */ 52