1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Timesys Corporation 4 * Copyright (C) 2015 General Electric Company 5 * Copyright (C) 2014 Advantech 6 * Copyright (C) 2012 Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the GE MX6Q Bx50v3 boards. 9 */ 10 11 #ifndef __GE_BX50V3_CONFIG_H 12 #define __GE_BX50V3_CONFIG_H 13 14 #include <asm/arch/imx-regs.h> 15 #include <asm/mach-imx/gpio.h> 16 17 #define CONFIG_BOARD_NAME "General Electric Bx50v3" 18 19 #define CONFIG_MXC_UART_BASE UART3_BASE 20 #define CONSOLE_DEV "ttymxc2" 21 22 #define CONFIG_SUPPORT_EMMC_BOOT 23 24 25 #include "mx6_common.h" 26 #include <linux/sizes.h> 27 28 #define CONFIG_CMDLINE_TAG 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 #define CONFIG_REVISION_TAG 32 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) 33 34 #define CONFIG_HW_WATCHDOG 35 #define CONFIG_IMX_WATCHDOG 36 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 37 38 #define CONFIG_MXC_UART 39 40 #define CONFIG_MXC_OCOTP 41 42 /* SATA Configs */ 43 #ifdef CONFIG_CMD_SATA 44 #define CONFIG_SYS_SATA_MAX_DEVICE 1 45 #define CONFIG_DWC_AHSATA_PORT_ID 0 46 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 47 #define CONFIG_LBA48 48 #endif 49 50 /* MMC Configs */ 51 #define CONFIG_FSL_USDHC 52 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 53 54 /* USB Configs */ 55 #ifdef CONFIG_USB 56 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 57 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 58 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 59 #define CONFIG_MXC_USB_FLAGS 0 60 61 #define CONFIG_USBD_HS 62 #define CONFIG_USB_GADGET_MASS_STORAGE 63 #endif 64 65 /* Networking Configs */ 66 #ifdef CONFIG_NET 67 #define CONFIG_FEC_MXC 68 #define IMX_FEC_BASE ENET_BASE_ADDR 69 #define CONFIG_FEC_XCV_TYPE RGMII 70 #define CONFIG_ETHPRIME "FEC" 71 #define CONFIG_FEC_MXC_PHYADDR 4 72 #define CONFIG_PHY_ATHEROS 73 #endif 74 75 /* Serial Flash */ 76 #ifdef CONFIG_CMD_SF 77 #define CONFIG_SF_DEFAULT_BUS 0 78 #define CONFIG_SF_DEFAULT_CS 0 79 #define CONFIG_SF_DEFAULT_SPEED 20000000 80 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 81 #endif 82 83 /* allow to overwrite serial and ethaddr */ 84 #define CONFIG_ENV_OVERWRITE 85 86 #define CONFIG_LOADADDR 0x12000000 87 88 #define CONFIG_EXTRA_ENV_SETTINGS \ 89 "bootcause=POR\0" \ 90 "bootlimit=10\0" \ 91 "image=/boot/fitImage\0" \ 92 "fdt_high=0xffffffff\0" \ 93 "dev=mmc\0" \ 94 "devnum=1\0" \ 95 "rootdev=mmcblk0p\0" \ 96 "quiet=quiet loglevel=0\0" \ 97 "console=" CONSOLE_DEV "\0" \ 98 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ 99 "ro rootwait cma=128M " \ 100 "bootcause=${bootcause} " \ 101 "${quiet} console=${console} ${rtc_status} " \ 102 "${videoargs}" "\0" \ 103 "doquiet=" \ 104 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ 105 "then setenv quiet; fi\0" \ 106 "hasfirstboot=" \ 107 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ 108 "/boot/bootcause/firstboot\0" \ 109 "swappartitions=" \ 110 "setexpr partnum 3 - ${partnum}\0" \ 111 "failbootcmd=" \ 112 "bx50_backlight_enable; " \ 113 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ 114 "echo $msg; " \ 115 "setenv stdout vga; " \ 116 "echo \"\n\n\n\n \" $msg; " \ 117 "setenv stdout serial; " \ 118 "mw.b 0x7000A000 0xbc; " \ 119 "mw.b 0x7000A001 0x00; " \ 120 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ 121 "altbootcmd=" \ 122 "run doquiet; " \ 123 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 124 "run hasfirstboot || setenv partnum 0; " \ 125 "if test ${partnum} != 0; then " \ 126 "setenv bootcause REVERT; " \ 127 "run swappartitions loadimage doboot; " \ 128 "fi; " \ 129 "run failbootcmd\0" \ 130 "loadimage=" \ 131 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ 132 "doboot=" \ 133 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ 134 "run setargs; " \ 135 "bootm ${loadaddr}#conf@${confidx}\0" \ 136 "tryboot=" \ 137 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 138 "run loadimage || run swappartitions && run loadimage || " \ 139 "setenv partnum 0 && echo MISSING IMAGE;" \ 140 "run doboot; " \ 141 "run failbootcmd\0" \ 142 143 #define CONFIG_MMCBOOTCOMMAND \ 144 "if mmc dev ${devnum}; then " \ 145 "run doquiet; " \ 146 "run tryboot; " \ 147 "fi; " \ 148 149 #define CONFIG_USBBOOTCOMMAND \ 150 "echo Unsupported; " \ 151 152 #ifdef CONFIG_CMD_USB 153 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND 154 #else 155 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 156 #endif 157 158 #define CONFIG_ARP_TIMEOUT 200UL 159 160 /* Miscellaneous configurable options */ 161 162 #define CONFIG_SYS_MEMTEST_START 0x10000000 163 #define CONFIG_SYS_MEMTEST_END 0x10010000 164 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 165 166 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 167 168 /* Physical Memory Map */ 169 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 170 171 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 172 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 173 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 174 175 #define CONFIG_SYS_INIT_SP_OFFSET \ 176 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 177 #define CONFIG_SYS_INIT_SP_ADDR \ 178 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 179 180 /* environment organization */ 181 #define CONFIG_ENV_SIZE (8 * 1024) 182 #define CONFIG_ENV_OFFSET (768 * 1024) 183 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 184 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 185 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 186 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 187 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 188 189 #define CONFIG_SYS_FSL_USDHC_NUM 3 190 191 /* Framebuffer */ 192 #define CONFIG_VIDEO 193 #ifdef CONFIG_VIDEO 194 #define CONFIG_VIDEO_IPUV3 195 #define CONFIG_CFB_CONSOLE 196 #define CONFIG_VGA_AS_SINGLE_DEVICE 197 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF 198 #define CONFIG_SYS_CONSOLE_BG_COL 0x00 199 #define CONFIG_HIDE_LOGO_VERSION 200 #define CONFIG_IMX_HDMI 201 #define CONFIG_IMX_VIDEO_SKIP 202 #define CONFIG_CMD_BMP 203 #endif 204 205 #define CONFIG_PWM_IMX 206 #define CONFIG_IMX6_PWM_PER_CLK 66000000 207 208 #define CONFIG_PCI 209 #define CONFIG_PCI_PNP 210 #define CONFIG_PCI_SCAN_SHOW 211 #define CONFIG_PCIE_IMX 212 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 213 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) 214 215 #define CONFIG_RTC_RX8010SJ 216 #define CONFIG_SYS_RTC_BUS_NUM 2 217 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 218 219 /* I2C Configs */ 220 #define CONFIG_SYS_I2C 221 #define CONFIG_SYS_I2C_MXC 222 #define CONFIG_SYS_I2C_SPEED 100000 223 #define CONFIG_SYS_I2C_MXC_I2C1 224 #define CONFIG_SYS_I2C_MXC_I2C2 225 #define CONFIG_SYS_I2C_MXC_I2C3 226 227 #define CONFIG_SYS_NUM_I2C_BUSES 11 228 #define CONFIG_SYS_I2C_MAX_HOPS 1 229 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 230 {1, {I2C_NULL_HOP} }, \ 231 {2, {I2C_NULL_HOP} }, \ 232 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ 233 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 234 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 235 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ 236 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ 237 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ 238 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ 239 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ 240 } 241 242 #define CONFIG_BCH 243 244 #endif /* __GE_BX50V3_CONFIG_H */ 245