1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Timesys Corporation 4 * Copyright (C) 2015 General Electric Company 5 * Copyright (C) 2014 Advantech 6 * Copyright (C) 2012 Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the GE MX6Q Bx50v3 boards. 9 */ 10 11 #ifndef __GE_BX50V3_CONFIG_H 12 #define __GE_BX50V3_CONFIG_H 13 14 #include <asm/arch/imx-regs.h> 15 #include <asm/mach-imx/gpio.h> 16 17 #define CONFIG_BOARD_NAME "General Electric Bx50v3" 18 19 #define CONFIG_MXC_UART_BASE UART3_BASE 20 #define CONSOLE_DEV "ttymxc2" 21 22 #define CONFIG_SUPPORT_EMMC_BOOT 23 24 25 #include "mx6_common.h" 26 #include <linux/sizes.h> 27 28 #define CONFIG_CMDLINE_TAG 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 #define CONFIG_REVISION_TAG 32 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) 33 34 #define CONFIG_HW_WATCHDOG 35 #define CONFIG_IMX_WATCHDOG 36 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 37 38 #define CONFIG_MXC_UART 39 40 #define CONFIG_MXC_OCOTP 41 42 /* SATA Configs */ 43 #ifdef CONFIG_CMD_SATA 44 #define CONFIG_SYS_SATA_MAX_DEVICE 1 45 #define CONFIG_DWC_AHSATA_PORT_ID 0 46 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 47 #define CONFIG_LBA48 48 #endif 49 50 /* MMC Configs */ 51 #define CONFIG_FSL_USDHC 52 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 53 54 /* USB Configs */ 55 #ifdef CONFIG_USB 56 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 57 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 58 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 59 #define CONFIG_MXC_USB_FLAGS 0 60 61 #define CONFIG_USBD_HS 62 #define CONFIG_USB_GADGET_MASS_STORAGE 63 #endif 64 65 /* Networking Configs */ 66 #ifdef CONFIG_NET 67 #define CONFIG_FEC_MXC 68 #define IMX_FEC_BASE ENET_BASE_ADDR 69 #define CONFIG_FEC_XCV_TYPE RGMII 70 #define CONFIG_ETHPRIME "FEC" 71 #define CONFIG_FEC_MXC_PHYADDR 4 72 #define CONFIG_PHY_ATHEROS 73 #endif 74 75 /* Serial Flash */ 76 #ifdef CONFIG_CMD_SF 77 #define CONFIG_SF_DEFAULT_BUS 0 78 #define CONFIG_SF_DEFAULT_CS 0 79 #define CONFIG_SF_DEFAULT_SPEED 20000000 80 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 81 #endif 82 83 /* allow to overwrite serial and ethaddr */ 84 #define CONFIG_ENV_OVERWRITE 85 86 #define CONFIG_LOADADDR 0x12000000 87 88 #define CONFIG_EXTRA_ENV_SETTINGS \ 89 "bootcause=POR\0" \ 90 "image=/boot/fitImage\0" \ 91 "fdt_high=0xffffffff\0" \ 92 "dev=mmc\0" \ 93 "devnum=1\0" \ 94 "rootdev=mmcblk0p\0" \ 95 "quiet=quiet loglevel=0\0" \ 96 "console=" CONSOLE_DEV "\0" \ 97 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ 98 "ro rootwait cma=128M " \ 99 "bootcause=${bootcause} " \ 100 "${quiet} console=${console} ${rtc_status} " \ 101 "${videoargs}" "\0" \ 102 "doquiet=" \ 103 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ 104 "then setenv quiet; fi\0" \ 105 "hasfirstboot=" \ 106 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ 107 "/boot/bootcause/firstboot\0" \ 108 "swappartitions=" \ 109 "setexpr partnum 3 - ${partnum}\0" \ 110 "failbootcmd=" \ 111 "bx50_backlight_enable; " \ 112 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ 113 "echo $msg; " \ 114 "setenv stdout vga; " \ 115 "echo \"\n\n\n\n \" $msg; " \ 116 "setenv stdout serial; " \ 117 "mw.b 0x7000A000 0xbc; " \ 118 "mw.b 0x7000A001 0x00; " \ 119 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ 120 "altbootcmd=" \ 121 "run doquiet; " \ 122 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 123 "run hasfirstboot || setenv partnum 0; " \ 124 "if test ${partnum} != 0; then " \ 125 "setenv bootcause REVERT; " \ 126 "run swappartitions loadimage doboot; " \ 127 "fi; " \ 128 "run failbootcmd\0" \ 129 "loadimage=" \ 130 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ 131 "doboot=" \ 132 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ 133 "run setargs; " \ 134 "bootm ${loadaddr}#conf@${confidx}\0" \ 135 "tryboot=" \ 136 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 137 "run loadimage || run swappartitions && run loadimage || " \ 138 "setenv partnum 0 && echo MISSING IMAGE;" \ 139 "run doboot; " \ 140 "run failbootcmd\0" \ 141 142 #define CONFIG_MMCBOOTCOMMAND \ 143 "if mmc dev ${devnum}; then " \ 144 "run doquiet; " \ 145 "run tryboot; " \ 146 "fi; " \ 147 148 #define CONFIG_USBBOOTCOMMAND \ 149 "echo Unsupported; " \ 150 151 #ifdef CONFIG_CMD_USB 152 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND 153 #else 154 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 155 #endif 156 157 #define CONFIG_ARP_TIMEOUT 200UL 158 159 /* Miscellaneous configurable options */ 160 161 #define CONFIG_SYS_MEMTEST_START 0x10000000 162 #define CONFIG_SYS_MEMTEST_END 0x10010000 163 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 164 165 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 166 167 /* Physical Memory Map */ 168 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 169 170 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 171 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 172 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 173 174 #define CONFIG_SYS_INIT_SP_OFFSET \ 175 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 176 #define CONFIG_SYS_INIT_SP_ADDR \ 177 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 178 179 /* environment organization */ 180 #define CONFIG_ENV_SIZE (8 * 1024) 181 #define CONFIG_ENV_OFFSET (768 * 1024) 182 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 183 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 184 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 185 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 186 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 187 188 #define CONFIG_SYS_FSL_USDHC_NUM 3 189 190 /* Framebuffer */ 191 #define CONFIG_VIDEO 192 #ifdef CONFIG_VIDEO 193 #define CONFIG_VIDEO_IPUV3 194 #define CONFIG_CFB_CONSOLE 195 #define CONFIG_VGA_AS_SINGLE_DEVICE 196 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF 197 #define CONFIG_SYS_CONSOLE_BG_COL 0x00 198 #define CONFIG_HIDE_LOGO_VERSION 199 #define CONFIG_IMX_HDMI 200 #define CONFIG_IMX_VIDEO_SKIP 201 #define CONFIG_CMD_BMP 202 #endif 203 204 #define CONFIG_PWM_IMX 205 #define CONFIG_IMX6_PWM_PER_CLK 66000000 206 207 #define CONFIG_PCI 208 #define CONFIG_PCI_PNP 209 #define CONFIG_PCI_SCAN_SHOW 210 #define CONFIG_PCIE_IMX 211 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 212 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) 213 214 #define CONFIG_RTC_RX8010SJ 215 #define CONFIG_SYS_RTC_BUS_NUM 2 216 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 217 218 /* I2C Configs */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_MXC 221 #define CONFIG_SYS_I2C_SPEED 100000 222 #define CONFIG_SYS_I2C_MXC_I2C1 223 #define CONFIG_SYS_I2C_MXC_I2C2 224 #define CONFIG_SYS_I2C_MXC_I2C3 225 226 #define CONFIG_SYS_NUM_I2C_BUSES 11 227 #define CONFIG_SYS_I2C_MAX_HOPS 1 228 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 229 {1, {I2C_NULL_HOP} }, \ 230 {2, {I2C_NULL_HOP} }, \ 231 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ 232 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 233 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 234 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ 235 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ 236 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ 237 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ 238 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ 239 } 240 241 #define CONFIG_BCH 242 243 #endif /* __GE_BX50V3_CONFIG_H */ 244