1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Timesys Corporation 4 * Copyright (C) 2015 General Electric Company 5 * Copyright (C) 2014 Advantech 6 * Copyright (C) 2012 Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the GE MX6Q Bx50v3 boards. 9 */ 10 11 #ifndef __GE_BX50V3_CONFIG_H 12 #define __GE_BX50V3_CONFIG_H 13 14 #include <asm/arch/imx-regs.h> 15 #include <asm/mach-imx/gpio.h> 16 17 #define CONFIG_BOARD_NAME "General Electric Bx50v3" 18 19 #define CONFIG_MXC_UART_BASE UART3_BASE 20 #define CONSOLE_DEV "ttymxc2" 21 22 #define CONFIG_SUPPORT_EMMC_BOOT 23 24 25 #include "mx6_common.h" 26 #include <linux/sizes.h> 27 28 #define CONFIG_CMDLINE_TAG 29 #define CONFIG_SETUP_MEMORY_TAGS 30 #define CONFIG_INITRD_TAG 31 #define CONFIG_REVISION_TAG 32 #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) 33 34 #define CONFIG_HW_WATCHDOG 35 #define CONFIG_IMX_WATCHDOG 36 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 37 38 #define CONFIG_MXC_UART 39 40 #define CONFIG_MXC_OCOTP 41 42 /* SATA Configs */ 43 #ifdef CONFIG_CMD_SATA 44 #define CONFIG_SYS_SATA_MAX_DEVICE 1 45 #define CONFIG_DWC_AHSATA_PORT_ID 0 46 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 47 #define CONFIG_LBA48 48 #endif 49 50 /* MMC Configs */ 51 #define CONFIG_FSL_USDHC 52 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 53 54 /* USB Configs */ 55 #ifdef CONFIG_USB 56 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 57 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 58 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 59 #define CONFIG_MXC_USB_FLAGS 0 60 61 #define CONFIG_USBD_HS 62 #define CONFIG_USB_GADGET_MASS_STORAGE 63 #endif 64 65 /* Networking Configs */ 66 #ifdef CONFIG_NET 67 #define CONFIG_FEC_MXC 68 #define CONFIG_MII 69 #define IMX_FEC_BASE ENET_BASE_ADDR 70 #define CONFIG_FEC_XCV_TYPE RGMII 71 #define CONFIG_ETHPRIME "FEC" 72 #define CONFIG_FEC_MXC_PHYADDR 4 73 #define CONFIG_PHY_ATHEROS 74 #endif 75 76 /* Serial Flash */ 77 #ifdef CONFIG_CMD_SF 78 #define CONFIG_SF_DEFAULT_BUS 0 79 #define CONFIG_SF_DEFAULT_CS 0 80 #define CONFIG_SF_DEFAULT_SPEED 20000000 81 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 82 #endif 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 87 #define CONFIG_LOADADDR 0x12000000 88 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "bootcause=POR\0" \ 91 "bootlimit=10\0" \ 92 "image=/boot/fitImage\0" \ 93 "fdt_high=0xffffffff\0" \ 94 "dev=mmc\0" \ 95 "devnum=1\0" \ 96 "rootdev=mmcblk0p\0" \ 97 "quiet=quiet loglevel=0\0" \ 98 "console=" CONSOLE_DEV "\0" \ 99 "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ 100 "ro rootwait cma=128M " \ 101 "bootcause=${bootcause} " \ 102 "${quiet} console=${console} ${rtc_status} " \ 103 "${videoargs}" "\0" \ 104 "doquiet=" \ 105 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ 106 "then setenv quiet; fi\0" \ 107 "hasfirstboot=" \ 108 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ 109 "/boot/bootcause/firstboot\0" \ 110 "swappartitions=" \ 111 "setexpr partnum 3 - ${partnum}\0" \ 112 "failbootcmd=" \ 113 "bx50_backlight_enable; " \ 114 "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ 115 "echo $msg; " \ 116 "setenv stdout vga; " \ 117 "echo \"\n\n\n\n \" $msg; " \ 118 "setenv stdout serial; " \ 119 "mw.b 0x7000A000 0xbc; " \ 120 "mw.b 0x7000A001 0x00; " \ 121 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ 122 "altbootcmd=" \ 123 "run doquiet; " \ 124 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 125 "run hasfirstboot || setenv partnum 0; " \ 126 "if test ${partnum} != 0; then " \ 127 "setenv bootcause REVERT; " \ 128 "run swappartitions loadimage doboot; " \ 129 "fi; " \ 130 "run failbootcmd\0" \ 131 "loadimage=" \ 132 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ 133 "doboot=" \ 134 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ 135 "run setargs; " \ 136 "bootm ${loadaddr}#conf@${confidx}\0" \ 137 "tryboot=" \ 138 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ 139 "run loadimage || run swappartitions && run loadimage || " \ 140 "setenv partnum 0 && echo MISSING IMAGE;" \ 141 "run doboot; " \ 142 "run failbootcmd\0" \ 143 144 #define CONFIG_MMCBOOTCOMMAND \ 145 "if mmc dev ${devnum}; then " \ 146 "run doquiet; " \ 147 "run tryboot; " \ 148 "fi; " \ 149 150 #define CONFIG_USBBOOTCOMMAND \ 151 "echo Unsupported; " \ 152 153 #ifdef CONFIG_CMD_USB 154 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND 155 #else 156 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 157 #endif 158 159 #define CONFIG_ARP_TIMEOUT 200UL 160 161 /* Miscellaneous configurable options */ 162 163 #define CONFIG_SYS_MEMTEST_START 0x10000000 164 #define CONFIG_SYS_MEMTEST_END 0x10010000 165 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 166 167 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 168 169 /* Physical Memory Map */ 170 #define CONFIG_NR_DRAM_BANKS 1 171 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 172 173 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 174 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 175 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 176 177 #define CONFIG_SYS_INIT_SP_OFFSET \ 178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_ADDR \ 180 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 181 182 /* environment organization */ 183 #define CONFIG_ENV_SIZE (8 * 1024) 184 #define CONFIG_ENV_OFFSET (768 * 1024) 185 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 186 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 187 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 188 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 189 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 190 191 #ifndef CONFIG_SYS_DCACHE_OFF 192 #endif 193 194 #define CONFIG_SYS_FSL_USDHC_NUM 3 195 196 /* Framebuffer */ 197 #define CONFIG_VIDEO 198 #ifdef CONFIG_VIDEO 199 #define CONFIG_VIDEO_IPUV3 200 #define CONFIG_CFB_CONSOLE 201 #define CONFIG_VGA_AS_SINGLE_DEVICE 202 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF 203 #define CONFIG_SYS_CONSOLE_BG_COL 0x00 204 #define CONFIG_HIDE_LOGO_VERSION 205 #define CONFIG_IMX_HDMI 206 #define CONFIG_IMX_VIDEO_SKIP 207 #define CONFIG_CMD_BMP 208 #endif 209 210 #define CONFIG_PWM_IMX 211 #define CONFIG_IMX6_PWM_PER_CLK 66000000 212 213 #define CONFIG_PCI 214 #define CONFIG_PCI_PNP 215 #define CONFIG_PCI_SCAN_SHOW 216 #define CONFIG_PCIE_IMX 217 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 218 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) 219 220 #define CONFIG_RTC_RX8010SJ 221 #define CONFIG_SYS_RTC_BUS_NUM 2 222 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 223 224 /* I2C Configs */ 225 #define CONFIG_SYS_I2C 226 #define CONFIG_SYS_I2C_MXC 227 #define CONFIG_SYS_I2C_SPEED 100000 228 #define CONFIG_SYS_I2C_MXC_I2C1 229 #define CONFIG_SYS_I2C_MXC_I2C2 230 #define CONFIG_SYS_I2C_MXC_I2C3 231 232 #define CONFIG_SYS_NUM_I2C_BUSES 11 233 #define CONFIG_SYS_I2C_MAX_HOPS 1 234 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 235 {1, {I2C_NULL_HOP} }, \ 236 {2, {I2C_NULL_HOP} }, \ 237 {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ 238 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 239 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 240 {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ 241 {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ 242 {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ 243 {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ 244 {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ 245 } 246 247 #define CONFIG_BCH 248 249 #endif /* __GE_BX50V3_CONFIG_H */ 250