1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the Espresso7420 board. 4 * Copyright (C) 2016 Samsung Electronics 5 * Thomas Abraham <thomas.ab@samsung.com> 6 */ 7 8 #ifndef __CONFIG_EXYNOS7420_COMMON_H 9 #define __CONFIG_EXYNOS7420_COMMON_H 10 11 /* High Level Configuration Options */ 12 #define CONFIG_SAMSUNG /* in a SAMSUNG core */ 13 #define CONFIG_EXYNOS7420 /* Exynos7 Family */ 14 #define CONFIG_S5P 15 16 #include <asm/arch/cpu.h> /* get chip and board defs */ 17 #include <linux/sizes.h> 18 19 #define CONFIG_ARCH_CPU_INIT 20 21 /* Size of malloc() pool before and after relocation */ 22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) 23 24 /* Miscellaneous configurable options */ 25 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 26 #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 27 28 /* Boot Argument Buffer Size */ 29 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 30 31 /* select serial console configuration */ 32 33 /* Timer input clock frequency */ 34 #define COUNTER_FREQUENCY 24000000 35 36 /* Device Tree */ 37 #define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" 38 39 /* IRAM Layout */ 40 #define CONFIG_IRAM_BASE 0x02100000 41 #define CONFIG_IRAM_SIZE 0x58000 42 #define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) 43 #define CPU_RELEASE_ADDR secondary_boot_addr 44 45 /* select serial console configuration */ 46 47 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 48 49 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 50 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 51 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 52 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 53 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 54 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 55 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 56 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 57 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 58 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 59 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 60 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 61 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 62 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 63 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 64 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 65 66 /* Configuration of ENV Blocks */ 67 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 68 69 #define BOOT_TARGET_DEVICES(func) \ 70 func(MMC, mmc, 1) \ 71 func(MMC, mmc, 0) \ 72 73 #ifndef MEM_LAYOUT_ENV_SETTINGS 74 #define MEM_LAYOUT_ENV_SETTINGS \ 75 "bootm_size=0x10000000\0" \ 76 "kernel_addr_r=0x42000000\0" \ 77 "fdt_addr_r=0x43000000\0" \ 78 "ramdisk_addr_r=0x43300000\0" \ 79 "scriptaddr=0x50000000\0" \ 80 "pxefile_addr_r=0x51000000\0" 81 #endif 82 83 #ifndef EXYNOS_DEVICE_SETTINGS 84 #define EXYNOS_DEVICE_SETTINGS \ 85 "stdin=serial\0" \ 86 "stdout=serial\0" \ 87 "stderr=serial\0" 88 #endif 89 90 #ifndef EXYNOS_FDTFILE_SETTING 91 #define EXYNOS_FDTFILE_SETTING 92 #endif 93 94 #define CONFIG_EXTRA_ENV_SETTINGS \ 95 EXYNOS_DEVICE_SETTINGS \ 96 EXYNOS_FDTFILE_SETTING \ 97 MEM_LAYOUT_ENV_SETTINGS 98 99 #endif /* __CONFIG_EXYNOS7420_COMMON_H */ 100