1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  *
4  * Configuration settings for the SAMSUNG EXYNOS5 board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
11 
12 #define CONFIG_EXYNOS5			/* Exynos5 Family */
13 
14 #include "exynos-common.h"
15 
16 #define CONFIG_EXYNOS_SPL
17 
18 #ifdef FTRACE
19 #define CONFIG_TRACE
20 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
21 #define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
22 #define CONFIG_TRACE_EARLY
23 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
24 #endif
25 
26 /* Enable ACE acceleration for SHA1 and SHA256 */
27 #define CONFIG_EXYNOS_ACE_SHA
28 
29 /* Power Down Modes */
30 #define S5P_CHECK_SLEEP			0x00000BAD
31 #define S5P_CHECK_DIDLE			0xBAD00000
32 #define S5P_CHECK_LPA			0xABAD0000
33 
34 /* Offset for inform registers */
35 #define INFORM0_OFFSET			0x800
36 #define INFORM1_OFFSET			0x804
37 #define INFORM2_OFFSET			0x808
38 #define INFORM3_OFFSET			0x80c
39 
40 /* select serial console configuration */
41 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
42 
43 /* Thermal Management Unit */
44 #define CONFIG_EXYNOS_TMU
45 
46 /* MMC SPL */
47 #define COPY_BL2_FNPTR_ADDR	0x02020030
48 #define CONFIG_SUPPORT_EMMC_BOOT
49 
50 /* specific .lds file */
51 
52 /* Boot Argument Buffer Size */
53 /* memtest works on */
54 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
55 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
56 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
57 
58 #define CONFIG_RD_LVL
59 
60 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
61 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
62 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
63 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
64 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
65 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
66 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
67 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
68 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
69 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
70 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
71 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
72 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
73 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
74 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
75 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
76 
77 #define CONFIG_SYS_MONITOR_BASE	0x00000000
78 
79 #define CONFIG_SYS_MMC_ENV_DEV		0
80 
81 #define CONFIG_SECURE_BL1_ONLY
82 
83 /* Secure FW size configuration */
84 #ifdef CONFIG_SECURE_BL1_ONLY
85 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
86 #else
87 #define CONFIG_SEC_FW_SIZE 0
88 #endif
89 
90 /* Configuration of BL1, BL2, ENV Blocks on mmc */
91 #define CONFIG_RES_BLOCK_SIZE	(512)
92 #define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
93 #define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
94 #define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
95 
96 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
97 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
98 
99 /* U-Boot copy size from boot Media to DRAM.*/
100 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
101 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
102 
103 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
104 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
105 
106 /* I2C */
107 #define CONFIG_SYS_I2C_S3C24X0
108 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
109 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
110 
111 /* SPI */
112 #ifdef CONFIG_SPI_FLASH
113 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
114 #define CONFIG_SF_DEFAULT_SPEED		50000000
115 #endif
116 
117 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
118 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
119 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
120 #define CONFIG_ENV_SPI_BUS	1
121 #define CONFIG_ENV_SPI_MAX_HZ	50000000
122 #endif
123 
124 /* Ethernet Controllor Driver */
125 #ifdef CONFIG_CMD_NET
126 #define CONFIG_SMC911X
127 #define CONFIG_SMC911X_BASE		0x5000000
128 #define CONFIG_SMC911X_16_BIT
129 #define CONFIG_ENV_SROM_BANK		1
130 #endif /*CONFIG_CMD_NET*/
131 
132 /* Enable Time Command */
133 
134 /* USB */
135 #define CONFIG_USB_HOST_ETHER
136 #define CONFIG_USB_ETHER_ASIX
137 #define CONFIG_USB_ETHER_SMSC95XX
138 #define CONFIG_USB_ETHER_RTL8152
139 
140 /* USB boot mode */
141 #define CONFIG_USB_BOOTING
142 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
143 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
144 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
145 
146 #define BOOT_TARGET_DEVICES(func) \
147 	func(MMC, mmc, 1) \
148 	func(MMC, mmc, 0) \
149 	func(PXE, pxe, na) \
150 	func(DHCP, dhcp, na)
151 
152 #include <config_distro_bootcmd.h>
153 
154 #ifndef MEM_LAYOUT_ENV_SETTINGS
155 /* 2GB RAM, bootm size of 256M, load scripts after that */
156 #define MEM_LAYOUT_ENV_SETTINGS \
157 	"bootm_size=0x10000000\0" \
158 	"kernel_addr_r=0x42000000\0" \
159 	"fdt_addr_r=0x43000000\0" \
160 	"ramdisk_addr_r=0x43300000\0" \
161 	"scriptaddr=0x50000000\0" \
162 	"pxefile_addr_r=0x51000000\0"
163 #endif
164 
165 #ifndef EXYNOS_DEVICE_SETTINGS
166 #define EXYNOS_DEVICE_SETTINGS \
167 	"stdin=serial\0" \
168 	"stdout=serial\0" \
169 	"stderr=serial\0"
170 #endif
171 
172 #ifndef EXYNOS_FDTFILE_SETTING
173 #define EXYNOS_FDTFILE_SETTING
174 #endif
175 
176 #define CONFIG_EXTRA_ENV_SETTINGS \
177 	EXYNOS_DEVICE_SETTINGS \
178 	EXYNOS_FDTFILE_SETTING \
179 	MEM_LAYOUT_ENV_SETTINGS \
180 	BOOTENV
181 
182 #endif	/* __CONFIG_EXYNOS5_COMMON_H */
183