1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  *
4  * Configuration settings for the SAMSUNG EXYNOS5 board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
11 
12 #define CONFIG_EXYNOS5			/* Exynos5 Family */
13 
14 #include "exynos-common.h"
15 
16 #define CONFIG_EXYNOS_SPL
17 
18 #ifdef FTRACE
19 #define CONFIG_TRACE
20 #define CONFIG_CMD_TRACE
21 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
22 #define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
23 #define CONFIG_TRACE_EARLY
24 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
25 #endif
26 
27 /* Enable ACE acceleration for SHA1 and SHA256 */
28 #define CONFIG_EXYNOS_ACE_SHA
29 
30 /* Power Down Modes */
31 #define S5P_CHECK_SLEEP			0x00000BAD
32 #define S5P_CHECK_DIDLE			0xBAD00000
33 #define S5P_CHECK_LPA			0xABAD0000
34 
35 /* Offset for inform registers */
36 #define INFORM0_OFFSET			0x800
37 #define INFORM1_OFFSET			0x804
38 #define INFORM2_OFFSET			0x808
39 #define INFORM3_OFFSET			0x80c
40 
41 /* select serial console configuration */
42 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
43 
44 /* Thermal Management Unit */
45 #define CONFIG_EXYNOS_TMU
46 
47 /* MMC SPL */
48 #define COPY_BL2_FNPTR_ADDR	0x02020030
49 #define CONFIG_SUPPORT_EMMC_BOOT
50 
51 /* specific .lds file */
52 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
53 
54 /* Boot Argument Buffer Size */
55 /* memtest works on */
56 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
57 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
58 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
59 
60 #define CONFIG_RD_LVL
61 
62 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
63 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
64 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
65 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
66 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
67 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
68 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
69 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
70 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
71 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
72 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
73 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
74 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
75 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
76 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
77 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
78 
79 #define CONFIG_SYS_MONITOR_BASE	0x00000000
80 
81 #define CONFIG_SYS_MMC_ENV_DEV		0
82 
83 #define CONFIG_SECURE_BL1_ONLY
84 
85 /* Secure FW size configuration */
86 #ifdef CONFIG_SECURE_BL1_ONLY
87 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
88 #else
89 #define CONFIG_SEC_FW_SIZE 0
90 #endif
91 
92 /* Configuration of BL1, BL2, ENV Blocks on mmc */
93 #define CONFIG_RES_BLOCK_SIZE	(512)
94 #define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
95 #define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
96 #define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
97 
98 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
99 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
100 
101 /* U-Boot copy size from boot Media to DRAM.*/
102 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
103 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
104 
105 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
106 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
107 
108 /* I2C */
109 #define CONFIG_SYS_I2C_S3C24X0
110 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
111 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
112 
113 /* SPI */
114 #ifdef CONFIG_SPI_FLASH
115 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
116 #define CONFIG_SF_DEFAULT_SPEED		50000000
117 #endif
118 
119 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
120 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
121 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
122 #define CONFIG_ENV_SPI_BUS	1
123 #define CONFIG_ENV_SPI_MAX_HZ	50000000
124 #endif
125 
126 /* Ethernet Controllor Driver */
127 #ifdef CONFIG_CMD_NET
128 #define CONFIG_SMC911X
129 #define CONFIG_SMC911X_BASE		0x5000000
130 #define CONFIG_SMC911X_16_BIT
131 #define CONFIG_ENV_SROM_BANK		1
132 #endif /*CONFIG_CMD_NET*/
133 
134 /* Enable Time Command */
135 
136 /* USB */
137 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
138 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
139 
140 #define CONFIG_USB_HOST_ETHER
141 #define CONFIG_USB_ETHER_ASIX
142 #define CONFIG_USB_ETHER_SMSC95XX
143 #define CONFIG_USB_ETHER_RTL8152
144 
145 /* USB boot mode */
146 #define CONFIG_USB_BOOTING
147 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
148 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
149 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
150 
151 #define BOOT_TARGET_DEVICES(func) \
152 	func(MMC, mmc, 1) \
153 	func(MMC, mmc, 0) \
154 	func(PXE, pxe, na) \
155 	func(DHCP, dhcp, na)
156 
157 #include <config_distro_bootcmd.h>
158 
159 #ifndef MEM_LAYOUT_ENV_SETTINGS
160 /* 2GB RAM, bootm size of 256M, load scripts after that */
161 #define MEM_LAYOUT_ENV_SETTINGS \
162 	"bootm_size=0x10000000\0" \
163 	"kernel_addr_r=0x42000000\0" \
164 	"fdt_addr_r=0x43000000\0" \
165 	"ramdisk_addr_r=0x43300000\0" \
166 	"scriptaddr=0x50000000\0" \
167 	"pxefile_addr_r=0x51000000\0"
168 #endif
169 
170 #ifndef EXYNOS_DEVICE_SETTINGS
171 #define EXYNOS_DEVICE_SETTINGS \
172 	"stdin=serial\0" \
173 	"stdout=serial\0" \
174 	"stderr=serial\0"
175 #endif
176 
177 #ifndef EXYNOS_FDTFILE_SETTING
178 #define EXYNOS_FDTFILE_SETTING
179 #endif
180 
181 #define CONFIG_EXTRA_ENV_SETTINGS \
182 	EXYNOS_DEVICE_SETTINGS \
183 	EXYNOS_FDTFILE_SETTING \
184 	MEM_LAYOUT_ENV_SETTINGS \
185 	BOOTENV
186 
187 #endif	/* __CONFIG_EXYNOS5_COMMON_H */
188