1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  *
4  * Configuration settings for the SAMSUNG EXYNOS5 board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
11 
12 #define CONFIG_EXYNOS5			/* Exynos5 Family */
13 
14 #include "exynos-common.h"
15 
16 #define CONFIG_SYS_CACHELINE_SIZE	64
17 #define CONFIG_EXYNOS_SPL
18 
19 #ifdef FTRACE
20 #define CONFIG_TRACE
21 #define CONFIG_CMD_TRACE
22 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
23 #define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
24 #define CONFIG_TRACE_EARLY
25 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
26 #endif
27 
28 /* Enable ACE acceleration for SHA1 and SHA256 */
29 #define CONFIG_EXYNOS_ACE_SHA
30 #define CONFIG_SHA_HW_ACCEL
31 
32 /* Power Down Modes */
33 #define S5P_CHECK_SLEEP			0x00000BAD
34 #define S5P_CHECK_DIDLE			0xBAD00000
35 #define S5P_CHECK_LPA			0xABAD0000
36 
37 /* Offset for inform registers */
38 #define INFORM0_OFFSET			0x800
39 #define INFORM1_OFFSET			0x804
40 #define INFORM2_OFFSET			0x808
41 #define INFORM3_OFFSET			0x80c
42 
43 /* select serial console configuration */
44 #define CONFIG_BAUDRATE			115200
45 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
46 #define CONFIG_SILENT_CONSOLE
47 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
48 #define CONFIG_CONSOLE_MUX
49 
50 #define CONFIG_CMD_HASH
51 
52 /* Thermal Management Unit */
53 #define CONFIG_EXYNOS_TMU
54 #define CONFIG_CMD_DTT
55 #define CONFIG_TMU_CMD_DTT
56 
57 /* MMC SPL */
58 #define COPY_BL2_FNPTR_ADDR	0x02020030
59 #define CONFIG_SUPPORT_EMMC_BOOT
60 
61 #define CONFIG_SPL_LIBCOMMON_SUPPORT
62 #define CONFIG_SPL_GPIO_SUPPORT
63 #define CONFIG_SPL_SERIAL_SUPPORT
64 #define CONFIG_SPL_LIBGENERIC_SUPPORT
65 
66 /* specific .lds file */
67 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
68 
69 /* Boot Argument Buffer Size */
70 /* memtest works on */
71 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
72 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
73 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
74 
75 #define CONFIG_RD_LVL
76 
77 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
78 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
79 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
80 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
81 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
82 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
83 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
84 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
85 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
86 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
87 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
88 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
89 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
90 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
91 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
92 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
93 
94 #define CONFIG_SYS_MONITOR_BASE	0x00000000
95 
96 #define CONFIG_SYS_MMC_ENV_DEV		0
97 
98 #define CONFIG_SECURE_BL1_ONLY
99 
100 /* Secure FW size configuration */
101 #ifdef CONFIG_SECURE_BL1_ONLY
102 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
103 #else
104 #define CONFIG_SEC_FW_SIZE 0
105 #endif
106 
107 /* Configuration of BL1, BL2, ENV Blocks on mmc */
108 #define CONFIG_RES_BLOCK_SIZE	(512)
109 #define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
110 #define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
111 #define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
112 
113 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
114 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
115 
116 /* U-Boot copy size from boot Media to DRAM.*/
117 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
118 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
119 
120 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
121 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
122 
123 /* I2C */
124 #define CONFIG_SYS_I2C_S3C24X0
125 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
126 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
127 #define CONFIG_I2C_EDID
128 
129 /* SPI */
130 #ifdef CONFIG_SPI_FLASH
131 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
132 #define CONFIG_SF_DEFAULT_SPEED		50000000
133 #endif
134 
135 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
136 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
137 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
138 #define CONFIG_ENV_SPI_BUS	1
139 #define CONFIG_ENV_SPI_MAX_HZ	50000000
140 #endif
141 
142 /* Ethernet Controllor Driver */
143 #ifdef CONFIG_CMD_NET
144 #define CONFIG_SMC911X
145 #define CONFIG_SMC911X_BASE		0x5000000
146 #define CONFIG_SMC911X_16_BIT
147 #define CONFIG_ENV_SROM_BANK		1
148 #endif /*CONFIG_CMD_NET*/
149 
150 /* SHA hashing */
151 #define CONFIG_CMD_HASH
152 #define CONFIG_HASH_VERIFY
153 #define CONFIG_SHA1
154 #define CONFIG_SHA256
155 
156 /* Enable Time Command */
157 
158 /* USB */
159 #define CONFIG_USB_STORAGE
160 #define CONFIG_USB_XHCI_DWC3
161 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
162 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
163 
164 #define CONFIG_USB_HOST_ETHER
165 #define CONFIG_USB_ETHER_ASIX
166 #define CONFIG_USB_ETHER_SMSC95XX
167 #define CONFIG_USB_ETHER_RTL8152
168 
169 /* USB boot mode */
170 #define CONFIG_USB_BOOTING
171 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
172 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
173 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
174 
175 #define BOOT_TARGET_DEVICES(func) \
176 	func(MMC, mmc, 1) \
177 	func(MMC, mmc, 0) \
178 	func(PXE, pxe, na) \
179 	func(DHCP, dhcp, na)
180 
181 #include <config_distro_bootcmd.h>
182 
183 #ifndef MEM_LAYOUT_ENV_SETTINGS
184 /* 2GB RAM, bootm size of 256M, load scripts after that */
185 #define MEM_LAYOUT_ENV_SETTINGS \
186 	"bootm_size=0x10000000\0" \
187 	"kernel_addr_r=0x42000000\0" \
188 	"fdt_addr_r=0x43000000\0" \
189 	"ramdisk_addr_r=0x43300000\0" \
190 	"scriptaddr=0x50000000\0" \
191 	"pxefile_addr_r=0x51000000\0"
192 #endif
193 
194 #ifndef EXYNOS_DEVICE_SETTINGS
195 #define EXYNOS_DEVICE_SETTINGS \
196 	"stdin=serial\0" \
197 	"stdout=serial\0" \
198 	"stderr=serial\0"
199 #endif
200 
201 #ifndef EXYNOS_FDTFILE_SETTING
202 #define EXYNOS_FDTFILE_SETTING
203 #endif
204 
205 #define CONFIG_EXTRA_ENV_SETTINGS \
206 	EXYNOS_DEVICE_SETTINGS \
207 	EXYNOS_FDTFILE_SETTING \
208 	MEM_LAYOUT_ENV_SETTINGS \
209 	BOOTENV
210 
211 #endif	/* __CONFIG_EXYNOS5_COMMON_H */
212