1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  *
4  * Configuration settings for the SAMSUNG EXYNOS5 board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
11 
12 #define CONFIG_EXYNOS5			/* Exynos5 Family */
13 
14 #include "exynos-common.h"
15 
16 #define CONFIG_SYS_CACHELINE_SIZE	64
17 #define CONFIG_EXYNOS_SPL
18 
19 /* Allow tracing to be enabled */
20 #define CONFIG_TRACE
21 #define CONFIG_CMD_TRACE
22 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
23 #define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
24 #define CONFIG_TRACE_EARLY
25 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
26 
27 
28 /* Enable ACE acceleration for SHA1 and SHA256 */
29 #define CONFIG_EXYNOS_ACE_SHA
30 #define CONFIG_SHA_HW_ACCEL
31 
32 /* Power Down Modes */
33 #define S5P_CHECK_SLEEP			0x00000BAD
34 #define S5P_CHECK_DIDLE			0xBAD00000
35 #define S5P_CHECK_LPA			0xABAD0000
36 
37 /* Offset for inform registers */
38 #define INFORM0_OFFSET			0x800
39 #define INFORM1_OFFSET			0x804
40 #define INFORM2_OFFSET			0x808
41 #define INFORM3_OFFSET			0x80c
42 
43 /* select serial console configuration */
44 #define CONFIG_BAUDRATE			115200
45 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
46 #define CONFIG_SILENT_CONSOLE
47 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
48 #define CONFIG_CONSOLE_MUX
49 
50 #define EXYNOS_DEVICE_SETTINGS \
51 		"stdin=serial\0" \
52 		"stdout=serial\0" \
53 		"stderr=serial\0"
54 
55 #define CONFIG_EXTRA_ENV_SETTINGS \
56 	EXYNOS_DEVICE_SETTINGS
57 
58 #define CONFIG_CMD_PING
59 #define CONFIG_CMD_ELF
60 #define CONFIG_CMD_NET
61 #define CONFIG_CMD_HASH
62 
63 /* Thermal Management Unit */
64 #define CONFIG_EXYNOS_TMU
65 #define CONFIG_CMD_DTT
66 #define CONFIG_TMU_CMD_DTT
67 
68 /* TPM */
69 #define CONFIG_TPM
70 #define CONFIG_CMD_TPM
71 #define CONFIG_TPM_TIS_I2C
72 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER	3
73 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR	0x20
74 
75 /* MMC SPL */
76 #define COPY_BL2_FNPTR_ADDR	0x02020030
77 #define CONFIG_SUPPORT_EMMC_BOOT
78 
79 #define CONFIG_SPL_LIBCOMMON_SUPPORT
80 #define CONFIG_SPL_GPIO_SUPPORT
81 
82 /* specific .lds file */
83 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
84 
85 /* Boot Argument Buffer Size */
86 /* memtest works on */
87 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
88 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
89 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
90 
91 #define CONFIG_RD_LVL
92 
93 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
94 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
95 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
96 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
97 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
98 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
99 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
100 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
101 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
102 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
103 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
104 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
105 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
106 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
107 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
108 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
109 
110 #define CONFIG_SYS_MONITOR_BASE	0x00000000
111 
112 #define CONFIG_SYS_MMC_ENV_DEV		0
113 
114 #define CONFIG_SECURE_BL1_ONLY
115 
116 /* Secure FW size configuration */
117 #ifdef CONFIG_SECURE_BL1_ONLY
118 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
119 #else
120 #define CONFIG_SEC_FW_SIZE 0
121 #endif
122 
123 /* Configuration of BL1, BL2, ENV Blocks on mmc */
124 #define CONFIG_RES_BLOCK_SIZE	(512)
125 #define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
126 #define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
127 #define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
128 
129 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
130 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
131 
132 /* U-boot copy size from boot Media to DRAM.*/
133 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
134 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
135 
136 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
137 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
138 
139 /* I2C */
140 #define CONFIG_SYS_I2C_INIT_BOARD
141 #define CONFIG_SYS_I2C
142 #define CONFIG_CMD_I2C
143 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
144 #define CONFIG_SYS_I2C_S3C24X0
145 #define CONFIG_I2C_MULTI_BUS
146 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
147 #define CONFIG_I2C_EDID
148 
149 /* SPI */
150 #ifdef CONFIG_SPI_FLASH
151 #define CONFIG_EXYNOS_SPI
152 #define CONFIG_CMD_SF
153 #define CONFIG_CMD_SPI
154 #define CONFIG_SPI_FLASH_WINBOND
155 #define CONFIG_SPI_FLASH_GIGADEVICE
156 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
157 #define CONFIG_SF_DEFAULT_SPEED		50000000
158 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
159 #define CONFIG_OF_SPI
160 #endif
161 
162 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
163 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
164 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
165 #define CONFIG_ENV_SPI_BUS	1
166 #define CONFIG_ENV_SPI_MAX_HZ	50000000
167 #endif
168 
169 /* Ethernet Controllor Driver */
170 #ifdef CONFIG_CMD_NET
171 #define CONFIG_SMC911X
172 #define CONFIG_SMC911X_BASE		0x5000000
173 #define CONFIG_SMC911X_16_BIT
174 #define CONFIG_ENV_SROM_BANK		1
175 #endif /*CONFIG_CMD_NET*/
176 
177 /* Enable PXE Support */
178 #ifdef CONFIG_CMD_NET
179 #define CONFIG_CMD_PXE
180 #define CONFIG_MENU
181 #endif
182 
183 /* SHA hashing */
184 #define CONFIG_CMD_HASH
185 #define CONFIG_HASH_VERIFY
186 #define CONFIG_SHA1
187 #define CONFIG_SHA256
188 
189 /* Enable Time Command */
190 #define CONFIG_CMD_TIME
191 
192 #define CONFIG_CMD_BOOTZ
193 
194 #define CONFIG_CMD_GPIO
195 
196 /* USB boot mode */
197 #define CONFIG_USB_BOOTING
198 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
199 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
200 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
201 
202 /* Enable FIT support and comparison */
203 #define CONFIG_FIT
204 #define CONFIG_FIT_BEST_MATCH
205 
206 #endif	/* __CONFIG_EXYNOS5_COMMON_H */
207