1 /*
2  * Copyright (C) 2013 Samsung Electronics
3  *
4  * Configuration settings for the SAMSUNG EXYNOS5 board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
11 
12 #define CONFIG_EXYNOS5			/* Exynos5 Family */
13 
14 #include "exynos-common.h"
15 
16 #define CONFIG_SYS_CACHELINE_SIZE	64
17 #define CONFIG_EXYNOS_SPL
18 
19 #ifdef FTRACE
20 #define CONFIG_TRACE
21 #define CONFIG_CMD_TRACE
22 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
23 #define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
24 #define CONFIG_TRACE_EARLY
25 #define CONFIG_TRACE_EARLY_ADDR		0x50000000
26 #endif
27 
28 /* Enable ACE acceleration for SHA1 and SHA256 */
29 #define CONFIG_EXYNOS_ACE_SHA
30 #define CONFIG_SHA_HW_ACCEL
31 
32 /* Power Down Modes */
33 #define S5P_CHECK_SLEEP			0x00000BAD
34 #define S5P_CHECK_DIDLE			0xBAD00000
35 #define S5P_CHECK_LPA			0xABAD0000
36 
37 /* Offset for inform registers */
38 #define INFORM0_OFFSET			0x800
39 #define INFORM1_OFFSET			0x804
40 #define INFORM2_OFFSET			0x808
41 #define INFORM3_OFFSET			0x80c
42 
43 /* select serial console configuration */
44 #define CONFIG_BAUDRATE			115200
45 #define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
46 #define CONFIG_SILENT_CONSOLE
47 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
48 #define CONFIG_CONSOLE_MUX
49 
50 #define CONFIG_CMD_HASH
51 
52 /* Thermal Management Unit */
53 #define CONFIG_EXYNOS_TMU
54 #define CONFIG_CMD_DTT
55 #define CONFIG_TMU_CMD_DTT
56 
57 /* TPM */
58 #define CONFIG_TPM
59 #define CONFIG_CMD_TPM
60 #define CONFIG_TPM_TIS_I2C
61 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER	3
62 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR	0x20
63 
64 /* MMC SPL */
65 #define COPY_BL2_FNPTR_ADDR	0x02020030
66 #define CONFIG_SUPPORT_EMMC_BOOT
67 
68 #define CONFIG_SPL_LIBCOMMON_SUPPORT
69 #define CONFIG_SPL_GPIO_SUPPORT
70 
71 /* specific .lds file */
72 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
73 
74 /* Boot Argument Buffer Size */
75 /* memtest works on */
76 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
77 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
78 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
79 
80 #define CONFIG_RD_LVL
81 
82 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
83 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
84 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
85 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
86 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
87 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
88 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
89 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
90 #define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
91 #define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
92 #define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
93 #define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
94 #define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
95 #define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
96 #define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
97 #define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
98 
99 #define CONFIG_SYS_MONITOR_BASE	0x00000000
100 
101 #define CONFIG_SYS_MMC_ENV_DEV		0
102 
103 #define CONFIG_SECURE_BL1_ONLY
104 
105 /* Secure FW size configuration */
106 #ifdef CONFIG_SECURE_BL1_ONLY
107 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
108 #else
109 #define CONFIG_SEC_FW_SIZE 0
110 #endif
111 
112 /* Configuration of BL1, BL2, ENV Blocks on mmc */
113 #define CONFIG_RES_BLOCK_SIZE	(512)
114 #define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
115 #define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
116 #define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
117 
118 #define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
119 #define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
120 
121 /* U-boot copy size from boot Media to DRAM.*/
122 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
123 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
124 
125 #define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
126 #define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
127 
128 /* I2C */
129 
130 /* TODO(sjg@chromium.org): Move these two options to Kconfig */
131 #define CONFIG_DM_I2C
132 #define CONFIG_DM_I2C_COMPAT
133 #define CONFIG_CMD_I2C
134 #define CONFIG_SYS_I2C_S3C24X0
135 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
136 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
137 #define CONFIG_I2C_EDID
138 
139 /* SPI */
140 #ifdef CONFIG_SPI_FLASH
141 #define CONFIG_EXYNOS_SPI
142 #define CONFIG_CMD_SF
143 #define CONFIG_CMD_SPI
144 #define CONFIG_SPI_FLASH_WINBOND
145 #define CONFIG_SPI_FLASH_GIGADEVICE
146 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
147 #define CONFIG_SF_DEFAULT_SPEED		50000000
148 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
149 #define CONFIG_OF_SPI
150 #endif
151 
152 /* Power */
153 #define CONFIG_POWER
154 #define CONFIG_POWER_I2C
155 
156 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
157 #define CONFIG_ENV_SPI_MODE	SPI_MODE_0
158 #define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
159 #define CONFIG_ENV_SPI_BUS	1
160 #define CONFIG_ENV_SPI_MAX_HZ	50000000
161 #endif
162 
163 /* Ethernet Controllor Driver */
164 #ifdef CONFIG_CMD_NET
165 #define CONFIG_SMC911X
166 #define CONFIG_SMC911X_BASE		0x5000000
167 #define CONFIG_SMC911X_16_BIT
168 #define CONFIG_ENV_SROM_BANK		1
169 #endif /*CONFIG_CMD_NET*/
170 
171 /* SHA hashing */
172 #define CONFIG_CMD_HASH
173 #define CONFIG_HASH_VERIFY
174 #define CONFIG_SHA1
175 #define CONFIG_SHA256
176 
177 /* Enable Time Command */
178 #define CONFIG_CMD_TIME
179 
180 #define CONFIG_CMD_GPIO
181 
182 /* USB */
183 #define CONFIG_CMD_USB
184 #define CONFIG_USB_STORAGE
185 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
186 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
187 
188 #define CONFIG_USB_HOST_ETHER
189 #define CONFIG_USB_ETHER_ASIX
190 #define CONFIG_USB_ETHER_SMSC95XX
191 
192 /* USB boot mode */
193 #define CONFIG_USB_BOOTING
194 #define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
195 #define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
196 #define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
197 
198 /* Enable FIT support and comparison */
199 #define CONFIG_FIT
200 #define CONFIG_FIT_BEST_MATCH
201 
202 
203 #define BOOT_TARGET_DEVICES(func) \
204 	func(MMC, mmc, 1) \
205 	func(MMC, mmc, 0) \
206 	func(PXE, pxe, na) \
207 	func(DHCP, dhcp, na)
208 
209 #include <config_distro_bootcmd.h>
210 
211 #ifndef MEM_LAYOUT_ENV_SETTINGS
212 /* 2GB RAM, bootm size of 256M, load scripts after that */
213 #define MEM_LAYOUT_ENV_SETTINGS \
214 	"bootm_size=0x10000000\0" \
215 	"kernel_addr_r=0x42000000\0" \
216 	"fdt_addr_r=0x43000000\0" \
217 	"ramdisk_addr_r=0x43300000\0" \
218 	"scriptaddr=0x50000000\0" \
219 	"pxefile_addr_r=0x51000000\0"
220 #endif
221 
222 #ifndef EXYNOS_DEVICE_SETTINGS
223 #define EXYNOS_DEVICE_SETTINGS \
224 	"stdin=serial\0" \
225 	"stdout=serial\0" \
226 	"stderr=serial\0"
227 #endif
228 
229 #ifndef EXYNOS_FDTFILE_SETTING
230 #define EXYNOS_FDTFILE_SETTING
231 #endif
232 
233 #define CONFIG_EXTRA_ENV_SETTINGS \
234 	EXYNOS_DEVICE_SETTINGS \
235 	EXYNOS_FDTFILE_SETTING \
236 	MEM_LAYOUT_ENV_SETTINGS \
237 	BOOTENV
238 
239 #endif	/* __CONFIG_EXYNOS5_COMMON_H */
240