1 /* 2 * (C) Copyright 2011 3 * egnite GmbH <info@egnite.de> 4 * 5 * Configuation settings for Ethernut 5 with AT91SAM9XE. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/hardware.h> 14 15 /* The first stage boot loader expects u-boot running at this address. */ 16 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ 17 18 /* The first stage boot loader takes care of low level initialization. */ 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 /* Set our official architecture number. */ 22 #define MACH_TYPE_ETHERNUT5 1971 23 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 24 25 /* CPU information */ 26 #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ 27 #define CONFIG_ARCH_CPU_INIT 28 29 /* ARM asynchronous clock */ 30 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 31 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 32 33 /* 32kB internal SRAM */ 34 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ 35 #define CONFIG_SRAM_SIZE (32 << 10) 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ 37 GENERATED_GBL_DATA_SIZE) 38 39 /* 128MB SDRAM in 1 bank */ 40 #define CONFIG_NR_DRAM_BANKS 1 41 #define CONFIG_SYS_SDRAM_BASE 0x20000000 42 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) 43 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 44 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 46 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 47 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ 48 - CONFIG_SYS_MALLOC_LEN) 49 50 /* 512kB on-chip NOR flash */ 51 # define CONFIG_SYS_MAX_FLASH_BANKS 1 52 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ 53 # define CONFIG_AT91_EFLASH 54 # define CONFIG_SYS_MAX_FLASH_SECT 32 55 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ 56 # define CONFIG_EFLASH_PROTSECTORS 1 57 58 /* 512kB DataFlash at NPCS0 */ 59 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 60 #define CONFIG_HAS_DATAFLASH 61 #define CONFIG_ATMEL_DATAFLASH_SPI 62 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 63 #define DATAFLASH_TCSS (0x1a << 16) 64 #define DATAFLASH_TCHS (0x1 << 24) 65 66 #define CONFIG_ENV_IS_IN_SPI_FLASH 67 #define CONFIG_ENV_OFFSET 0x3DE000 68 #define CONFIG_ENV_SECT_SIZE (132 << 10) 69 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 70 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ 71 + CONFIG_ENV_OFFSET) 72 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ 73 + 0x042000) 74 75 /* SPI */ 76 #define CONFIG_ATMEL_SPI 77 #define AT91_SPI_CLK 15000000 78 79 /* Serial port */ 80 #define CONFIG_ATMEL_USART 81 #define CONFIG_USART3 /* USART 3 is DBGU */ 82 #define CONFIG_BAUDRATE 115200 83 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 84 #define CONFIG_USART_ID ATMEL_ID_SYS 85 86 /* Misc. hardware drivers */ 87 #define CONFIG_AT91_GPIO 88 89 /* Command line configuration */ 90 #define CONFIG_CMD_JFFS2 91 #define CONFIG_CMD_MTDPARTS 92 #define CONFIG_CMD_NAND 93 94 #ifndef MINIMAL_LOADER 95 #define CONFIG_CMD_BSP 96 #define CONFIG_CMD_DATE 97 #define CONFIG_CMD_REISER 98 #define CONFIG_CMD_SAVES 99 #define CONFIG_CMD_UBIFS 100 #define CONFIG_CMD_UNZIP 101 #endif 102 103 /* NAND flash */ 104 #ifdef CONFIG_CMD_NAND 105 #define CONFIG_SYS_MAX_NAND_DEVICE 1 106 #define CONFIG_SYS_NAND_BASE 0x40000000 107 #define CONFIG_SYS_NAND_DBW_8 108 #define CONFIG_NAND_ATMEL 109 /* our ALE is AD21 */ 110 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 111 /* our CLE is AD22 */ 112 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 113 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 114 #endif 115 116 /* JFFS2 */ 117 #ifdef CONFIG_CMD_JFFS2 118 #define CONFIG_JFFS2_CMDLINE 119 #define CONFIG_JFFS2_NAND 120 #endif 121 122 /* Ethernet */ 123 #define CONFIG_NET_RETRY_COUNT 20 124 #define CONFIG_MACB 125 #define CONFIG_RMII 126 #define CONFIG_PHY_ID 0 127 #define CONFIG_MACB_SEARCH_PHY 128 129 /* MMC */ 130 #ifdef CONFIG_CMD_MMC 131 #define CONFIG_MMC 132 #define CONFIG_GENERIC_MMC 133 #define CONFIG_GENERIC_ATMEL_MCI 134 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 135 #endif 136 137 /* USB */ 138 #ifdef CONFIG_CMD_USB 139 #define CONFIG_USB_ATMEL 140 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 141 #define CONFIG_USB_OHCI_NEW 142 #define CONFIG_SYS_USB_OHCI_CPU_INIT 143 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 144 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" 145 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 146 #endif 147 148 /* RTC */ 149 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) 150 #define CONFIG_RTC_PCF8563 151 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 152 #endif 153 154 /* I2C */ 155 #define CONFIG_SYS_MAX_I2C_BUS 1 156 157 #define CONFIG_SYS_I2C 158 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 159 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 160 #define CONFIG_SYS_I2C_SOFT_SLAVE 0 161 162 #define I2C_SOFT_DECLARATIONS 163 164 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 165 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 166 167 #define I2C_INIT { \ 168 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ 169 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 170 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ 171 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ 172 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 173 } 174 175 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) 176 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) 177 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 178 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) 179 #define I2C_DELAY udelay(100) 180 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) 181 182 /* DHCP/BOOTP options */ 183 #ifdef CONFIG_CMD_DHCP 184 #define CONFIG_BOOTP_BOOTFILESIZE 185 #define CONFIG_BOOTP_BOOTPATH 186 #define CONFIG_BOOTP_GATEWAY 187 #define CONFIG_BOOTP_HOSTNAME 188 #define CONFIG_SYS_AUTOLOAD "n" 189 #endif 190 191 /* File systems */ 192 #define CONFIG_MTD_DEVICE 193 #define CONFIG_MTD_PARTITIONS 194 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) 195 #define MTDIDS_DEFAULT "nand0=atmel_nand" 196 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" 197 #endif 198 #if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \ 199 defined(CONFIG_CMD_USB) || defined(CONFIG_MMC) 200 #define CONFIG_DOS_PARTITION 201 #endif 202 #define CONFIG_LZO 203 #define CONFIG_RBTREE 204 205 /* Boot command */ 206 #define CONFIG_CMDLINE_TAG 207 #define CONFIG_SETUP_MEMORY_TAGS 208 #define CONFIG_INITRD_TAG 209 #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" 210 #if defined(CONFIG_CMD_NAND) 211 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 212 "root=/dev/mtdblock0 " \ 213 MTDPARTS_DEFAULT \ 214 " rw rootfstype=jffs2" 215 #endif 216 217 /* Misc. u-boot settings */ 218 #define CONFIG_SYS_CBSIZE 256 219 #define CONFIG_SYS_MAXARGS 16 220 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ 221 + sizeof(CONFIG_SYS_PROMPT)) 222 #define CONFIG_SYS_LONGHELP 223 #define CONFIG_CMDLINE_EDITING 224 225 #endif 226