1 /* 2 * (C) Copyright 2011 3 * egnite GmbH <info@egnite.de> 4 * 5 * Configuation settings for Ethernut 5 with AT91SAM9XE. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/hardware.h> 14 15 /* The first stage boot loader expects u-boot running at this address. */ 16 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ 17 18 /* The first stage boot loader takes care of low level initialization. */ 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 /* Set our official architecture number. */ 22 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 23 24 /* CPU information */ 25 #define CONFIG_ARCH_CPU_INIT 26 27 /* ARM asynchronous clock */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 29 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 30 31 /* 32kB internal SRAM */ 32 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ 33 #define CONFIG_SRAM_SIZE (32 << 10) 34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ 35 GENERATED_GBL_DATA_SIZE) 36 37 /* 128MB SDRAM in 1 bank */ 38 #define CONFIG_NR_DRAM_BANKS 1 39 #define CONFIG_SYS_SDRAM_BASE 0x20000000 40 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) 41 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 42 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 44 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 45 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ 46 - CONFIG_SYS_MALLOC_LEN) 47 48 /* 512kB on-chip NOR flash */ 49 # define CONFIG_SYS_MAX_FLASH_BANKS 1 50 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ 51 # define CONFIG_AT91_EFLASH 52 # define CONFIG_SYS_MAX_FLASH_SECT 32 53 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ 54 # define CONFIG_EFLASH_PROTSECTORS 1 55 56 57 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 58 #define CONFIG_ENV_OFFSET 0x3DE000 59 #define CONFIG_ENV_SIZE (132 << 10) 60 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 61 #define CONFIG_ENV_SPI_MAX_HZ 15000000 62 63 #ifndef MINIMAL_LOADER 64 #define CONFIG_CMD_REISER 65 #define CONFIG_CMD_SAVES 66 #endif 67 68 /* NAND flash */ 69 #ifdef CONFIG_CMD_NAND 70 #define CONFIG_SYS_MAX_NAND_DEVICE 1 71 #define CONFIG_SYS_NAND_BASE 0x40000000 72 #define CONFIG_SYS_NAND_DBW_8 73 #define CONFIG_NAND_ATMEL 74 /* our ALE is AD21 */ 75 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 76 /* our CLE is AD22 */ 77 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 78 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 79 #endif 80 81 /* JFFS2 */ 82 #ifdef CONFIG_CMD_JFFS2 83 #define CONFIG_JFFS2_CMDLINE 84 #define CONFIG_JFFS2_NAND 85 #endif 86 87 /* Ethernet */ 88 #define CONFIG_NET_RETRY_COUNT 20 89 #define CONFIG_MACB 90 #define CONFIG_RMII 91 #define CONFIG_PHY_ID 0 92 #define CONFIG_MACB_SEARCH_PHY 93 94 /* MMC */ 95 #ifdef CONFIG_CMD_MMC 96 #define CONFIG_GENERIC_ATMEL_MCI 97 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 98 #endif 99 100 /* USB */ 101 #ifdef CONFIG_CMD_USB 102 #define CONFIG_USB_ATMEL 103 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 104 #define CONFIG_USB_OHCI_NEW 105 #define CONFIG_SYS_USB_OHCI_CPU_INIT 106 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 107 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" 108 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 109 #endif 110 111 /* RTC */ 112 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) 113 #define CONFIG_RTC_PCF8563 114 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 115 #endif 116 117 /* I2C */ 118 #define CONFIG_SYS_MAX_I2C_BUS 1 119 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 122 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 123 #define CONFIG_SYS_I2C_SOFT_SLAVE 0 124 125 #define I2C_SOFT_DECLARATIONS 126 127 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 128 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 129 130 #define I2C_INIT { \ 131 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ 132 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 133 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ 134 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ 135 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 136 } 137 138 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) 139 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) 140 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 141 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) 142 #define I2C_DELAY udelay(100) 143 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) 144 145 /* DHCP/BOOTP options */ 146 #ifdef CONFIG_CMD_DHCP 147 #define CONFIG_BOOTP_BOOTFILESIZE 148 #define CONFIG_BOOTP_BOOTPATH 149 #define CONFIG_BOOTP_GATEWAY 150 #define CONFIG_BOOTP_HOSTNAME 151 #define CONFIG_SYS_AUTOLOAD "n" 152 #endif 153 154 /* File systems */ 155 #define CONFIG_MTD_DEVICE 156 #define CONFIG_MTD_PARTITIONS 157 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) 158 #define MTDIDS_DEFAULT "nand0=atmel_nand" 159 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" 160 #endif 161 162 /* Boot command */ 163 #define CONFIG_CMDLINE_TAG 164 #define CONFIG_SETUP_MEMORY_TAGS 165 #define CONFIG_INITRD_TAG 166 #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ 167 "sf read 0x22000000 0xc6000 0x294000; " \ 168 "bootm 0x22000000" 169 #if defined(CONFIG_CMD_NAND) 170 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 171 "root=/dev/mtdblock0 " \ 172 MTDPARTS_DEFAULT \ 173 " rw rootfstype=jffs2" 174 #endif 175 176 /* Misc. u-boot settings */ 177 #define CONFIG_SYS_CBSIZE 256 178 #define CONFIG_SYS_MAXARGS 16 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ 180 + sizeof(CONFIG_SYS_PROMPT)) 181 #define CONFIG_SYS_LONGHELP 182 #define CONFIG_CMDLINE_EDITING 183 184 #endif 185