1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 4 * egnite GmbH <info@egnite.de> 5 * 6 * Configuation settings for Ethernut 5 with AT91SAM9XE. 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/hardware.h> 13 14 /* The first stage boot loader expects u-boot running at this address. */ 15 16 /* The first stage boot loader takes care of low level initialization. */ 17 #define CONFIG_SKIP_LOWLEVEL_INIT 18 19 /* Set our official architecture number. */ 20 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 21 22 /* CPU information */ 23 #define CONFIG_ARCH_CPU_INIT 24 25 /* ARM asynchronous clock */ 26 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 28 29 /* 32kB internal SRAM */ 30 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ 31 #define CONFIG_SRAM_SIZE (32 << 10) 32 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ 33 GENERATED_GBL_DATA_SIZE) 34 35 /* 128MB SDRAM in 1 bank */ 36 #define CONFIG_NR_DRAM_BANKS 1 37 #define CONFIG_SYS_SDRAM_BASE 0x20000000 38 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) 39 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 40 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 42 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 43 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ 44 - CONFIG_SYS_MALLOC_LEN) 45 46 /* 512kB on-chip NOR flash */ 47 # define CONFIG_SYS_MAX_FLASH_BANKS 1 48 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ 49 # define CONFIG_AT91_EFLASH 50 # define CONFIG_SYS_MAX_FLASH_SECT 32 51 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ 52 # define CONFIG_EFLASH_PROTSECTORS 1 53 54 55 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 56 #define CONFIG_ENV_OFFSET 0x3DE000 57 #define CONFIG_ENV_SIZE (132 << 10) 58 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 59 #define CONFIG_ENV_SPI_MAX_HZ 15000000 60 61 /* NAND flash */ 62 #ifdef CONFIG_CMD_NAND 63 #define CONFIG_SYS_MAX_NAND_DEVICE 1 64 #define CONFIG_SYS_NAND_BASE 0x40000000 65 #define CONFIG_SYS_NAND_DBW_8 66 /* our ALE is AD21 */ 67 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 68 /* our CLE is AD22 */ 69 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 70 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 71 #endif 72 73 /* JFFS2 */ 74 #ifdef CONFIG_CMD_JFFS2 75 #define CONFIG_JFFS2_CMDLINE 76 #define CONFIG_JFFS2_NAND 77 #endif 78 79 /* Ethernet */ 80 #define CONFIG_NET_RETRY_COUNT 20 81 #define CONFIG_MACB 82 #define CONFIG_RMII 83 #define CONFIG_PHY_ID 0 84 #define CONFIG_MACB_SEARCH_PHY 85 86 /* MMC */ 87 #ifdef CONFIG_CMD_MMC 88 #define CONFIG_GENERIC_ATMEL_MCI 89 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 90 #endif 91 92 /* USB */ 93 #ifdef CONFIG_CMD_USB 94 #define CONFIG_USB_ATMEL 95 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 96 #define CONFIG_USB_OHCI_NEW 97 #define CONFIG_SYS_USB_OHCI_CPU_INIT 98 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 99 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" 100 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 101 #endif 102 103 /* RTC */ 104 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) 105 #define CONFIG_RTC_PCF8563 106 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 107 #endif 108 109 /* I2C */ 110 #define CONFIG_SYS_MAX_I2C_BUS 1 111 112 #define CONFIG_SYS_I2C 113 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 114 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 115 #define CONFIG_SYS_I2C_SOFT_SLAVE 0 116 117 #define I2C_SOFT_DECLARATIONS 118 119 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 120 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 121 122 #define I2C_INIT { \ 123 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ 124 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 125 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ 126 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ 127 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 128 } 129 130 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) 131 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) 132 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 133 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) 134 #define I2C_DELAY udelay(100) 135 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) 136 137 /* DHCP/BOOTP options */ 138 #ifdef CONFIG_CMD_DHCP 139 #define CONFIG_BOOTP_BOOTFILESIZE 140 #define CONFIG_SYS_AUTOLOAD "n" 141 #endif 142 143 /* File systems */ 144 145 /* Boot command */ 146 #define CONFIG_CMDLINE_TAG 147 #define CONFIG_SETUP_MEMORY_TAGS 148 #define CONFIG_INITRD_TAG 149 #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ 150 "sf read 0x22000000 0xc6000 0x294000; " \ 151 "bootm 0x22000000" 152 153 /* Misc. u-boot settings */ 154 155 #endif 156