1 /* 2 * (C) Copyright 2011 3 * egnite GmbH <info@egnite.de> 4 * 5 * Configuation settings for Ethernut 5 with AT91SAM9XE. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include <asm/hardware.h> 30 31 /* The first stage boot loader expects u-boot running at this address. */ 32 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ 33 34 /* The first stage boot loader takes care of low level initialization. */ 35 #define CONFIG_SKIP_LOWLEVEL_INIT 36 37 /* Set our official architecture number. */ 38 #define MACH_TYPE_ETHERNUT5 1971 39 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 40 41 /* CPU information */ 42 #define CONFIG_ARM926EJS 43 #define CONFIG_AT91FAMILY 44 #define CONFIG_DISPLAY_CPUINFO /* Display at console. */ 45 #define CONFIG_ARCH_CPU_INIT 46 47 /* ARM asynchronous clock */ 48 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 49 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 50 #define CONFIG_SYS_HZ 1000 51 #undef CONFIG_USE_IRQ /* Running w/o interrupts */ 52 53 /* 32kB internal SRAM */ 54 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ 55 #define CONFIG_SRAM_SIZE (32 << 10) 56 #define CONFIG_STACKSIZE (CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE) 57 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_STACKSIZE) 58 59 /* 128MB SDRAM in 1 bank */ 60 #define CONFIG_NR_DRAM_BANKS 1 61 #define CONFIG_SYS_SDRAM_BASE 0x20000000 62 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) 63 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 64 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 65 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 66 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 67 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ 68 - CONFIG_SYS_MALLOC_LEN) 69 70 /* 512kB on-chip NOR flash */ 71 # define CONFIG_SYS_MAX_FLASH_BANKS 1 72 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ 73 # define CONFIG_AT91_EFLASH 74 # define CONFIG_SYS_MAX_FLASH_SECT 32 75 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ 76 # define CONFIG_EFLASH_PROTSECTORS 1 77 78 /* 512kB DataFlash at NPCS0 */ 79 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 80 #define CONFIG_HAS_DATAFLASH 81 #define CONFIG_SPI_FLASH 82 #define CONFIG_SPI_FLASH_ATMEL 83 #define CONFIG_ATMEL_DATAFLASH_SPI 84 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 85 #define DATAFLASH_TCSS (0x1a << 16) 86 #define DATAFLASH_TCHS (0x1 << 24) 87 88 #define CONFIG_ENV_IS_IN_SPI_FLASH 89 #define CONFIG_ENV_OFFSET 0x3DE000 90 #define CONFIG_ENV_SECT_SIZE (132 << 10) 91 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 92 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ 93 + CONFIG_ENV_OFFSET) 94 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ 95 + 0x042000) 96 97 /* SPI */ 98 #define CONFIG_ATMEL_SPI 99 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) 100 #define AT91_SPI_CLK 15000000 101 102 /* Serial port */ 103 #define CONFIG_ATMEL_USART 104 #define CONFIG_USART3 /* USART 3 is DBGU */ 105 #define CONFIG_BAUDRATE 115200 106 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 107 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 108 #define CONFIG_USART_ID ATMEL_ID_SYS 109 110 /* Misc. hardware drivers */ 111 #define CONFIG_AT91_GPIO 112 113 /* Command line configuration */ 114 #include <config_cmd_default.h> 115 #undef CONFIG_CMD_BDI 116 #undef CONFIG_CMD_FPGA 117 #undef CONFIG_CMD_LOADS 118 119 #define CONFIG_CMD_JFFS2 120 #define CONFIG_CMD_MII 121 #define CONFIG_CMD_MTDPARTS 122 #define CONFIG_CMD_NAND 123 #define CONFIG_CMD_SPI 124 125 #ifdef MINIMAL_LOADER 126 #undef CONFIG_CMD_CONSOLE 127 #undef CONFIG_CMD_EDITENV 128 #undef CONFIG_CMD_IMI 129 #undef CONFIG_CMD_ITEST 130 #undef CONFIG_CMD_IMLS 131 #undef CONFIG_CMD_LOADB 132 #undef CONFIG_CMD_LOADS 133 #undef CONFIG_CMD_NFS 134 #undef CONFIG_CMD_SETGETDCR 135 #undef CONFIG_CMD_XIMG 136 #else 137 #define CONFIG_CMD_ASKENV 138 #define CONFIG_CMD_BSP 139 #define CONFIG_CMD_CACHE 140 #define CONFIG_CMD_CDP 141 #define CONFIG_CMD_DATE 142 #define CONFIG_CMD_DHCP 143 #define CONFIG_CMD_DNS 144 #define CONFIG_CMD_EXT2 145 #define CONFIG_CMD_FAT 146 #define CONFIG_CMD_I2C 147 #define CONFIG_CMD_MMC 148 #define CONFIG_CMD_PING 149 #define CONFIG_CMD_RARP 150 #define CONFIG_CMD_REISER 151 #define CONFIG_CMD_SAVES 152 #define CONFIG_CMD_SETEXPR 153 #define CONFIG_CMD_SF 154 #define CONFIG_CMD_SNTP 155 #define CONFIG_CMD_UBI 156 #define CONFIG_CMD_UBIFS 157 #define CONFIG_CMD_UNZIP 158 #define CONFIG_CMD_USB 159 #endif 160 161 /* NAND flash */ 162 #ifdef CONFIG_CMD_NAND 163 #define CONFIG_SYS_MAX_NAND_DEVICE 1 164 #define CONFIG_SYS_NAND_BASE 0x40000000 165 #define CONFIG_SYS_NAND_DBW_8 166 #define CONFIG_NAND_ATMEL 167 /* our ALE is AD21 */ 168 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 169 /* our CLE is AD22 */ 170 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 171 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 172 #endif 173 174 /* JFFS2 */ 175 #ifdef CONFIG_CMD_JFFS2 176 #define CONFIG_MTD_NAND_ECC_JFFS2 177 #define CONFIG_JFFS2_CMDLINE 178 #define CONFIG_JFFS2_NAND 179 #endif 180 181 /* Ethernet */ 182 #define CONFIG_NET_RETRY_COUNT 20 183 #define CONFIG_MACB 184 #define CONFIG_RMII 185 #define CONFIG_PHY_ID 0 186 #define CONFIG_MACB_SEARCH_PHY 187 188 /* MMC */ 189 #ifdef CONFIG_CMD_MMC 190 #define CONFIG_MMC 191 #define CONFIG_GENERIC_MMC 192 #define CONFIG_GENERIC_ATMEL_MCI 193 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 194 #endif 195 196 /* USB */ 197 #ifdef CONFIG_CMD_USB 198 #define CONFIG_USB_ATMEL 199 #define CONFIG_USB_OHCI_NEW 200 #define CONFIG_SYS_USB_OHCI_CPU_INIT 201 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 202 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" 203 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 204 #define CONFIG_USB_STORAGE 205 #endif 206 207 /* RTC */ 208 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) 209 #define CONFIG_RTC_PCF8563 210 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 211 #endif 212 213 /* I2C */ 214 #define CONFIG_SYS_MAX_I2C_BUS 1 215 #define CONFIG_SYS_I2C_SLAVE 0 216 #define CONFIG_SYS_I2C_SPEED 100000 217 218 #define CONFIG_SOFT_I2C 219 #define I2C_SOFT_DECLARATIONS 220 221 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 222 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 223 224 #define I2C_INIT { \ 225 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ 226 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 227 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ 228 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ 229 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 230 } 231 232 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) 233 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) 234 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 235 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) 236 #define I2C_DELAY udelay(100) 237 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) 238 239 /* DHCP/BOOTP options */ 240 #ifdef CONFIG_CMD_DHCP 241 #define CONFIG_BOOTP_BOOTFILESIZE 242 #define CONFIG_BOOTP_BOOTPATH 243 #define CONFIG_BOOTP_GATEWAY 244 #define CONFIG_BOOTP_HOSTNAME 245 #define CONFIG_SYS_AUTOLOAD "n" 246 #endif 247 248 /* File systems */ 249 #define CONFIG_MTD_DEVICE 250 #define CONFIG_MTD_PARTITIONS 251 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) 252 #define MTDIDS_DEFAULT "nand0=atmel_nand" 253 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" 254 #endif 255 #if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \ 256 defined(CONFIG_CMD_USB) || defined(CONFIG_MMC) 257 #define CONFIG_DOS_PARTITION 258 #endif 259 #define CONFIG_LZO 260 #define CONFIG_RBTREE 261 262 /* Boot command */ 263 #define CONFIG_BOOTDELAY 3 264 #define CONFIG_CMDLINE_TAG 265 #define CONFIG_SETUP_MEMORY_TAGS 266 #define CONFIG_INITRD_TAG 267 #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" 268 #if defined(CONFIG_CMD_NAND) 269 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 270 "root=/dev/mtdblock0 " \ 271 MTDPARTS_DEFAULT \ 272 " rw rootfstype=jffs2" 273 #endif 274 275 /* Misc. u-boot settings */ 276 #define CONFIG_SYS_PROMPT "U-Boot> " 277 #define CONFIG_SYS_HUSH_PARSER 278 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 279 #define CONFIG_SYS_CBSIZE 256 280 #define CONFIG_SYS_MAXARGS 16 281 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ 282 + sizeof(CONFIG_SYS_PROMPT)) 283 #define CONFIG_SYS_LONGHELP 284 #define CONFIG_CMDLINE_EDITING 285 286 #endif 287