1 /* 2 * (C) Copyright 2011 3 * egnite GmbH <info@egnite.de> 4 * 5 * Configuation settings for Ethernut 5 with AT91SAM9XE. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/hardware.h> 14 15 /* The first stage boot loader expects u-boot running at this address. */ 16 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ 17 18 /* The first stage boot loader takes care of low level initialization. */ 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 /* Set our official architecture number. */ 22 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 23 24 /* CPU information */ 25 #define CONFIG_ARCH_CPU_INIT 26 27 /* ARM asynchronous clock */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 29 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 30 31 /* 32kB internal SRAM */ 32 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ 33 #define CONFIG_SRAM_SIZE (32 << 10) 34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ 35 GENERATED_GBL_DATA_SIZE) 36 37 /* 128MB SDRAM in 1 bank */ 38 #define CONFIG_NR_DRAM_BANKS 1 39 #define CONFIG_SYS_SDRAM_BASE 0x20000000 40 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) 41 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 42 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 44 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 45 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ 46 - CONFIG_SYS_MALLOC_LEN) 47 48 /* 512kB on-chip NOR flash */ 49 # define CONFIG_SYS_MAX_FLASH_BANKS 1 50 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ 51 # define CONFIG_AT91_EFLASH 52 # define CONFIG_SYS_MAX_FLASH_SECT 32 53 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ 54 # define CONFIG_EFLASH_PROTSECTORS 1 55 56 /* 512kB DataFlash at NPCS0 */ 57 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 58 #define CONFIG_HAS_DATAFLASH 59 #define CONFIG_ATMEL_DATAFLASH_SPI 60 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 61 #define DATAFLASH_TCSS (0x1a << 16) 62 #define DATAFLASH_TCHS (0x1 << 24) 63 64 #define CONFIG_ENV_OFFSET 0x3DE000 65 #define CONFIG_ENV_SECT_SIZE (132 << 10) 66 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 67 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ 68 + CONFIG_ENV_OFFSET) 69 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ 70 + 0x042000) 71 72 /* SPI */ 73 #define CONFIG_ATMEL_SPI 74 #define AT91_SPI_CLK 15000000 75 76 /* Serial port */ 77 #define CONFIG_ATMEL_USART 78 #define CONFIG_USART3 /* USART 3 is DBGU */ 79 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 80 #define CONFIG_USART_ID ATMEL_ID_SYS 81 82 /* Misc. hardware drivers */ 83 #define CONFIG_AT91_GPIO 84 85 #ifndef MINIMAL_LOADER 86 #define CONFIG_CMD_REISER 87 #define CONFIG_CMD_SAVES 88 #endif 89 90 /* NAND flash */ 91 #ifdef CONFIG_CMD_NAND 92 #define CONFIG_SYS_MAX_NAND_DEVICE 1 93 #define CONFIG_SYS_NAND_BASE 0x40000000 94 #define CONFIG_SYS_NAND_DBW_8 95 #define CONFIG_NAND_ATMEL 96 /* our ALE is AD21 */ 97 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 98 /* our CLE is AD22 */ 99 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 100 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 101 #endif 102 103 /* JFFS2 */ 104 #ifdef CONFIG_CMD_JFFS2 105 #define CONFIG_JFFS2_CMDLINE 106 #define CONFIG_JFFS2_NAND 107 #endif 108 109 /* Ethernet */ 110 #define CONFIG_NET_RETRY_COUNT 20 111 #define CONFIG_MACB 112 #define CONFIG_RMII 113 #define CONFIG_PHY_ID 0 114 #define CONFIG_MACB_SEARCH_PHY 115 116 /* MMC */ 117 #ifdef CONFIG_CMD_MMC 118 #define CONFIG_GENERIC_ATMEL_MCI 119 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 120 #endif 121 122 /* USB */ 123 #ifdef CONFIG_CMD_USB 124 #define CONFIG_USB_ATMEL 125 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 126 #define CONFIG_USB_OHCI_NEW 127 #define CONFIG_SYS_USB_OHCI_CPU_INIT 128 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 129 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" 130 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 131 #endif 132 133 /* RTC */ 134 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) 135 #define CONFIG_RTC_PCF8563 136 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 137 #endif 138 139 /* I2C */ 140 #define CONFIG_SYS_MAX_I2C_BUS 1 141 142 #define CONFIG_SYS_I2C 143 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 144 #define CONFIG_SYS_I2C_SOFT_SPEED 100000 145 #define CONFIG_SYS_I2C_SOFT_SLAVE 0 146 147 #define I2C_SOFT_DECLARATIONS 148 149 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 150 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 151 152 #define I2C_INIT { \ 153 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ 154 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 155 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ 156 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ 157 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 158 } 159 160 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) 161 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) 162 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 163 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) 164 #define I2C_DELAY udelay(100) 165 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) 166 167 /* DHCP/BOOTP options */ 168 #ifdef CONFIG_CMD_DHCP 169 #define CONFIG_BOOTP_BOOTFILESIZE 170 #define CONFIG_BOOTP_BOOTPATH 171 #define CONFIG_BOOTP_GATEWAY 172 #define CONFIG_BOOTP_HOSTNAME 173 #define CONFIG_SYS_AUTOLOAD "n" 174 #endif 175 176 /* File systems */ 177 #define CONFIG_MTD_DEVICE 178 #define CONFIG_MTD_PARTITIONS 179 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) 180 #define MTDIDS_DEFAULT "nand0=atmel_nand" 181 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" 182 #endif 183 184 /* Boot command */ 185 #define CONFIG_CMDLINE_TAG 186 #define CONFIG_SETUP_MEMORY_TAGS 187 #define CONFIG_INITRD_TAG 188 #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" 189 #if defined(CONFIG_CMD_NAND) 190 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 191 "root=/dev/mtdblock0 " \ 192 MTDPARTS_DEFAULT \ 193 " rw rootfstype=jffs2" 194 #endif 195 196 /* Misc. u-boot settings */ 197 #define CONFIG_SYS_CBSIZE 256 198 #define CONFIG_SYS_MAXARGS 16 199 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ 200 + sizeof(CONFIG_SYS_PROMPT)) 201 #define CONFIG_SYS_LONGHELP 202 #define CONFIG_CMDLINE_EDITING 203 204 #endif 205