1 /* 2 * Configuation settings for the ESPT-GIGA board 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ESPT_H 11 #define __ESPT_H 12 13 #define CONFIG_CPU_SH7763 1 14 #define CONFIG_ESPT 1 15 #define __LITTLE_ENDIAN 1 16 17 /* 18 * Command line configuration. 19 */ 20 #define CONFIG_CMD_SDRAM 21 #define CONFIG_CMD_ENV 22 23 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" 24 #define CONFIG_ENV_OVERWRITE 1 25 26 #define CONFIG_DISPLAY_BOARDINFO 27 #undef CONFIG_SHOW_BOOT_PROGRESS 28 29 /* SCIF */ 30 #define CONFIG_SCIF_CONSOLE 1 31 #define CONFIG_BAUDRATE 115200 32 #define CONFIG_CONS_SCIF0 1 33 34 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 35 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 36 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 37 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 38 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 39 #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments 40 passed to kernel */ 41 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate 42 settings for this board */ 43 44 /* SDRAM */ 45 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 46 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 47 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 48 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 49 50 /* Flash(NOR) S29JL064H */ 51 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 52 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 53 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 54 #define CONFIG_SYS_MAX_FLASH_SECT (150) 55 56 /* U-Boot setting */ 57 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 58 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 59 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 60 /* Size of DRAM reserved for malloc() use */ 61 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 62 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 63 64 #define CONFIG_SYS_FLASH_CFI 65 #define CONFIG_FLASH_CFI_DRIVER 66 #undef CONFIG_SYS_FLASH_QUIET_TEST 67 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 68 /* Timeout for Flash erase operations (in ms) */ 69 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 70 /* Timeout for Flash write operations (in ms) */ 71 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 72 /* Timeout for Flash set sector lock bit operations (in ms) */ 73 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 74 /* Timeout for Flash clear lock bit operations (in ms) */ 75 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 76 /* Use hardware flash sectors protection instead of U-Boot software protection */ 77 #undef CONFIG_SYS_FLASH_PROTECTION 78 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 79 #define CONFIG_ENV_IS_IN_FLASH 80 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 81 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 82 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 83 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 84 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 85 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 86 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 87 88 /* Clock */ 89 #define CONFIG_SYS_CLK_FREQ 66666666 90 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 91 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 92 #define CONFIG_SYS_TMU_CLK_DIV 4 93 94 /* Ether */ 95 #define CONFIG_SH_ETHER 1 96 #define CONFIG_SH_ETHER_USE_PORT (1) 97 #define CONFIG_SH_ETHER_PHY_ADDR (0x00) 98 #define CONFIG_PHYLIB 99 #define CONFIG_BITBANGMII 100 #define CONFIG_BITBANGMII_MULTI 101 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 102 103 #endif /* __SH7763RDP_H */ 104