1 /* 2 * Configuation settings for the ESPT-GIGA board 3 * 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ESPT_H 11 #define __ESPT_H 12 13 #define CONFIG_SH 1 14 #define CONFIG_SH4 1 15 #define CONFIG_CPU_SH7763 1 16 #define CONFIG_ESPT 1 17 #define __LITTLE_ENDIAN 1 18 19 /* 20 * Command line configuration. 21 */ 22 #define CONFIG_CMD_SDRAM 23 #define CONFIG_CMD_FLASH 24 #define CONFIG_CMD_MEMORY 25 #define CONFIG_CMD_NET 26 #define CONFIG_CMD_MII 27 #define CONFIG_CMD_PING 28 #define CONFIG_CMD_ENV 29 #define CONFIG_CMD_NFS 30 #define CONFIG_CMD_SAVEENV 31 32 #define CONFIG_BOOTDELAY -1 33 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" 34 #define CONFIG_ENV_OVERWRITE 1 35 36 #define CONFIG_VERSION_VARIABLE 37 #undef CONFIG_SHOW_BOOT_PROGRESS 38 39 /* SCIF */ 40 #define CONFIG_SCIF_CONSOLE 1 41 #define CONFIG_BAUDRATE 115200 42 #define CONFIG_CONS_SCIF0 1 43 44 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 45 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 46 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 47 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 48 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 49 #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments 50 passed to kernel */ 51 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate 52 settings for this board */ 53 54 /* SDRAM */ 55 #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 56 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 57 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 58 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 59 60 /* Flash(NOR) S29JL064H */ 61 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 62 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 63 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 64 #define CONFIG_SYS_MAX_FLASH_SECT (150) 65 66 /* U-boot setting */ 67 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 68 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 69 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 70 /* Size of DRAM reserved for malloc() use */ 71 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 72 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 73 74 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_FLASH_CFI_DRIVER 76 #undef CONFIG_SYS_FLASH_QUIET_TEST 77 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 78 /* Timeout for Flash erase operations (in ms) */ 79 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 80 /* Timeout for Flash write operations (in ms) */ 81 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 82 /* Timeout for Flash set sector lock bit operations (in ms) */ 83 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 84 /* Timeout for Flash clear lock bit operations (in ms) */ 85 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 86 /* Use hardware flash sectors protection instead of U-Boot software protection */ 87 #undef CONFIG_SYS_FLASH_PROTECTION 88 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 89 #define CONFIG_ENV_IS_IN_FLASH 90 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 91 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 92 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 93 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 94 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 95 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 96 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 97 98 /* Clock */ 99 #define CONFIG_SYS_CLK_FREQ 66666666 100 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 101 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 102 #define CONFIG_SYS_TMU_CLK_DIV 4 103 104 /* Ether */ 105 #define CONFIG_SH_ETHER 1 106 #define CONFIG_SH_ETHER_USE_PORT (1) 107 #define CONFIG_SH_ETHER_PHY_ADDR (0x00) 108 #define CONFIG_PHYLIB 109 #define CONFIG_BITBANGMII 110 #define CONFIG_BITBANGMII_MULTI 111 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 112 113 #endif /* __SH7763RDP_H */ 114