1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 274d9c16aSNobuhiro Iwamatsu /* 374d9c16aSNobuhiro Iwamatsu * Configuation settings for the ESPT-GIGA board 474d9c16aSNobuhiro Iwamatsu * 574d9c16aSNobuhiro Iwamatsu * Copyright (C) 2008 Renesas Solutions Corp. 674d9c16aSNobuhiro Iwamatsu * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 774d9c16aSNobuhiro Iwamatsu */ 874d9c16aSNobuhiro Iwamatsu 974d9c16aSNobuhiro Iwamatsu #ifndef __ESPT_H 1074d9c16aSNobuhiro Iwamatsu #define __ESPT_H 1174d9c16aSNobuhiro Iwamatsu 1274d9c16aSNobuhiro Iwamatsu #define CONFIG_CPU_SH7763 1 1374d9c16aSNobuhiro Iwamatsu #define __LITTLE_ENDIAN 1 1474d9c16aSNobuhiro Iwamatsu 1574d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_OVERWRITE 1 1674d9c16aSNobuhiro Iwamatsu 1718a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO 1874d9c16aSNobuhiro Iwamatsu #undef CONFIG_SHOW_BOOT_PROGRESS 1974d9c16aSNobuhiro Iwamatsu 2074d9c16aSNobuhiro Iwamatsu /* SCIF */ 2174d9c16aSNobuhiro Iwamatsu #define CONFIG_CONS_SCIF0 1 2274d9c16aSNobuhiro Iwamatsu 2374d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 2474d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate 2574d9c16aSNobuhiro Iwamatsu settings for this board */ 2674d9c16aSNobuhiro Iwamatsu 2774d9c16aSNobuhiro Iwamatsu /* SDRAM */ 2874d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 2974d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 3074d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 3174d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 3274d9c16aSNobuhiro Iwamatsu 3374d9c16aSNobuhiro Iwamatsu /* Flash(NOR) S29JL064H */ 3474d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_BASE (0xA0000000) 3574d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 3674d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_BANKS (1) 3774d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MAX_FLASH_SECT (150) 3874d9c16aSNobuhiro Iwamatsu 39a187559eSBin Meng /* U-Boot setting */ 4074d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 4174d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 4274d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 4374d9c16aSNobuhiro Iwamatsu /* Size of DRAM reserved for malloc() use */ 4474d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 4574d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 4674d9c16aSNobuhiro Iwamatsu 4774d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_CFI 4874d9c16aSNobuhiro Iwamatsu #define CONFIG_FLASH_CFI_DRIVER 4974d9c16aSNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_QUIET_TEST 5074d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 5174d9c16aSNobuhiro Iwamatsu /* Timeout for Flash erase operations (in ms) */ 5274d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 5374d9c16aSNobuhiro Iwamatsu /* Timeout for Flash write operations (in ms) */ 5474d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 5574d9c16aSNobuhiro Iwamatsu /* Timeout for Flash set sector lock bit operations (in ms) */ 5674d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 5774d9c16aSNobuhiro Iwamatsu /* Timeout for Flash clear lock bit operations (in ms) */ 5874d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 5974d9c16aSNobuhiro Iwamatsu /* Use hardware flash sectors protection instead of U-Boot software protection */ 6074d9c16aSNobuhiro Iwamatsu #undef CONFIG_SYS_FLASH_PROTECTION 6174d9c16aSNobuhiro Iwamatsu #undef CONFIG_SYS_DIRECT_FLASH_TFTP 6274d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_SECT_SIZE (128 * 1024) 6374d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 6474d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 6574d9c16aSNobuhiro Iwamatsu /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 6674d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 6774d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 6874d9c16aSNobuhiro Iwamatsu #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 6974d9c16aSNobuhiro Iwamatsu 7074d9c16aSNobuhiro Iwamatsu /* Clock */ 7174d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ 66666666 72684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 73684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 7474d9c16aSNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 7574d9c16aSNobuhiro Iwamatsu 7674d9c16aSNobuhiro Iwamatsu /* Ether */ 7774d9c16aSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT (1) 7874d9c16aSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR (0x00) 7925a028bbSYoshihiro Shimoda #define CONFIG_BITBANGMII 8025a028bbSYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI 81a80a6619SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 8274d9c16aSNobuhiro Iwamatsu 8374d9c16aSNobuhiro Iwamatsu #endif /* __SH7763RDP_H */ 84