1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_TEXT_BASE 0xffff0000 21 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 22 #define CONFIG_SPL_STACK 0x00020000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 25 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 27 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 28 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 29 #define CONFIG_SYS_UBOOT_START 0x00800000 30 #define CONFIG_SYS_TEXT_BASE 0x00800000 31 32 /* 33 * High Level Configuration Options (easy to change) 34 */ 35 36 #define CONFIG_MARVELL 1 37 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 38 #define CONFIG_88F5182 1 /* SOC Name */ 39 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 40 41 #include <asm/arch/orion5x.h> 42 /* 43 * CLKs configurations 44 */ 45 46 /* 47 * Board-specific values for Orion5x MPP low level init: 48 * - MPPs 12 to 15 are SATA LEDs (mode 5) 49 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 50 * MPP16 to MPP19, mode 0 for others 51 */ 52 53 #define ORION5X_MPP0_7 0x00000003 54 #define ORION5X_MPP8_15 0x55550000 55 #define ORION5X_MPP16_23 0x00005555 56 57 /* 58 * Board-specific values for Orion5x GPIO low level init: 59 * - GPIO3 is input (RTC interrupt) 60 * - GPIO16 is Power LED control (0 = on, 1 = off) 61 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 62 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 63 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 64 * - GPIO22 is SATA disk power status () 65 * - GPIO23 is supply status for SATA disk () 66 * - GPIO24 is supply control for board (write 1 to power off) 67 * Last GPIO is 25, further bits are supposed to be 0. 68 * Enable mask has ones for INPUT, 0 for OUTPUT. 69 * Default is LED ON, board ON :) 70 */ 71 72 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 73 #define ORION5X_GPIO_OUT_VALUE 0x00000000 74 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 75 76 /* 77 * NS16550 Configuration 78 */ 79 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 82 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 83 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 84 85 /* 86 * Serial Port configuration 87 * The following definitions let you select what serial you want to use 88 * for your console driver. 89 */ 90 91 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 92 #define CONFIG_SYS_BAUDRATE_TABLE \ 93 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 94 95 /* 96 * FLASH configuration 97 */ 98 99 #define CONFIG_SYS_FLASH_CFI 100 #define CONFIG_FLASH_CFI_DRIVER 101 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 102 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 103 #define CONFIG_SYS_FLASH_BASE 0xfff80000 104 105 /* auto boot */ 106 107 /* 108 * For booting Linux, the board info and command line data 109 * have to be in the first 8 MB of memory, since this is 110 * the maximum mapped by the Linux kernel during initialization. 111 */ 112 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 113 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 114 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 115 116 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 118 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 119 /* 120 * Commands configuration 121 */ 122 123 /* 124 * Network 125 */ 126 127 #ifdef CONFIG_CMD_NET 128 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 129 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 130 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 131 #define CONFIG_PHY_BASE_ADR 0x8 132 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 133 #define CONFIG_NETCONSOLE /* include NetConsole support */ 134 #define CONFIG_MII /* expose smi ove miiphy interface */ 135 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 136 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 137 #endif 138 139 /* 140 * IDE 141 */ 142 #ifdef CONFIG_IDE 143 #define __io 144 #define CONFIG_IDE_PREINIT 145 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 146 #define CONFIG_MVSATA_IDE 147 #define CONFIG_MVSATA_IDE_USE_PORT1 148 /* Needs byte-swapping for ATA data register */ 149 #define CONFIG_IDE_SWAP_IO 150 /* Data, registers and alternate blocks are at the same offset */ 151 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 152 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 153 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 154 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 155 #define CONFIG_SYS_ATA_STRIDE 4 156 /* Controller supports 48-bits LBA addressing */ 157 #define CONFIG_LBA48 158 /* A single bus, a single device */ 159 #define CONFIG_SYS_IDE_MAXBUS 1 160 #define CONFIG_SYS_IDE_MAXDEVICE 1 161 /* ATA registers base is at SATA controller base */ 162 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 163 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 164 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 165 /* end of IDE defines */ 166 #endif /* CMD_IDE */ 167 168 /* 169 * Common USB/EHCI configuration 170 */ 171 #ifdef CONFIG_CMD_USB 172 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 173 #define CONFIG_SUPPORT_VFAT 174 #endif /* CONFIG_CMD_USB */ 175 176 /* 177 * I2C related stuff 178 */ 179 #ifdef CONFIG_CMD_I2C 180 #define CONFIG_SYS_I2C 181 #define CONFIG_SYS_I2C_MVTWSI 182 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 183 #define CONFIG_SYS_I2C_SLAVE 0x0 184 #define CONFIG_SYS_I2C_SPEED 100000 185 #endif 186 187 /* 188 * Environment variables configurations 189 */ 190 #define CONFIG_ENV_IS_IN_FLASH 1 191 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 192 #define CONFIG_ENV_SIZE 0x2000 193 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 194 195 /* 196 * Size of malloc() pool 197 */ 198 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 199 200 /* 201 * Other required minimal configurations 202 */ 203 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 204 #define CONFIG_NR_DRAM_BANKS 1 205 206 #define CONFIG_SYS_LOAD_ADDR 0x00800000 207 #define CONFIG_SYS_MEMTEST_START 0x00400000 208 #define CONFIG_SYS_MEMTEST_END 0x007fffff 209 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 210 #define CONFIG_SYS_MAXARGS 16 211 212 /* Enable command line editing */ 213 #define CONFIG_CMDLINE_EDITING 214 215 /* provide extensive help */ 216 #define CONFIG_SYS_LONGHELP 217 218 /* additions for new relocation code, must be added to all boards */ 219 #define CONFIG_SYS_SDRAM_BASE 0 220 #define CONFIG_SYS_INIT_SP_ADDR \ 221 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 222 223 #endif /* _CONFIG_EDMINIV2_H */ 224