1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* general settings */ 16 #define CONFIG_SYS_GENERIC_BOARD 17 18 /* 19 * SPL 20 */ 21 22 #define CONFIG_SPL_FRAMEWORK 23 #define CONFIG_SPL_LIBGENERIC_SUPPORT 24 #define CONFIG_SPL_LIBCOMMON_SUPPORT 25 #define CONFIG_SPL_SERIAL_SUPPORT 26 #define CONFIG_SPL_NOR_SUPPORT 27 #define CONFIG_SPL_TEXT_BASE 0xffff0000 28 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 29 #define CONFIG_SPL_STACK 0x00020000 30 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 31 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 32 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 33 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 34 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 35 #define CONFIG_SPL_BOARD_INIT 36 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 37 #define CONFIG_SYS_UBOOT_START 0x00800000 38 #define CONFIG_SYS_TEXT_BASE 0x00800000 39 40 /* 41 * Version number information 42 */ 43 44 #define CONFIG_IDENT_STRING " EDMiniV2" 45 46 /* 47 * High Level Configuration Options (easy to change) 48 */ 49 50 #define CONFIG_MARVELL 1 51 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 52 #define CONFIG_88F5182 1 /* SOC Name */ 53 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 54 55 #include <asm/arch/orion5x.h> 56 /* 57 * CLKs configurations 58 */ 59 60 /* 61 * Board-specific values for Orion5x MPP low level init: 62 * - MPPs 12 to 15 are SATA LEDs (mode 5) 63 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 64 * MPP16 to MPP19, mode 0 for others 65 */ 66 67 #define ORION5X_MPP0_7 0x00000003 68 #define ORION5X_MPP8_15 0x55550000 69 #define ORION5X_MPP16_23 0x00005555 70 71 /* 72 * Board-specific values for Orion5x GPIO low level init: 73 * - GPIO3 is input (RTC interrupt) 74 * - GPIO16 is Power LED control (0 = on, 1 = off) 75 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 76 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 77 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 78 * - GPIO22 is SATA disk power status () 79 * - GPIO23 is supply status for SATA disk () 80 * - GPIO24 is supply control for board (write 1 to power off) 81 * Last GPIO is 25, further bits are supposed to be 0. 82 * Enable mask has ones for INPUT, 0 for OUTPUT. 83 * Default is LED ON, board ON :) 84 */ 85 86 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 87 #define ORION5X_GPIO_OUT_VALUE 0x00000000 88 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 89 90 /* 91 * NS16550 Configuration 92 */ 93 94 #define CONFIG_SYS_NS16550 95 #define CONFIG_SYS_NS16550_SERIAL 96 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 97 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 98 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 99 100 /* 101 * Serial Port configuration 102 * The following definitions let you select what serial you want to use 103 * for your console driver. 104 */ 105 106 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 107 #define CONFIG_BAUDRATE 115200 108 #define CONFIG_SYS_BAUDRATE_TABLE \ 109 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 110 111 /* 112 * FLASH configuration 113 */ 114 115 #define CONFIG_SYS_FLASH_CFI 116 #define CONFIG_FLASH_CFI_DRIVER 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 119 #define CONFIG_SYS_FLASH_BASE 0xfff80000 120 121 /* auto boot */ 122 #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ 123 124 /* 125 * For booting Linux, the board info and command line data 126 * have to be in the first 8 MB of memory, since this is 127 * the maximum mapped by the Linux kernel during initialization. 128 */ 129 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 130 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 131 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 132 133 #define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ 134 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 136 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 137 /* 138 * Commands configuration - using default command set for now 139 */ 140 #include <config_cmd_default.h> 141 #define CONFIG_CMD_IDE 142 #define CONFIG_CMD_I2C 143 #define CONFIG_CMD_USB 144 145 /* 146 * Network 147 */ 148 149 #ifdef CONFIG_CMD_NET 150 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 151 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 152 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 153 #define CONFIG_PHY_BASE_ADR 0x8 154 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 155 #define CONFIG_NETCONSOLE /* include NetConsole support */ 156 #define CONFIG_MII /* expose smi ove miiphy interface */ 157 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 158 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 159 #endif 160 161 /* 162 * IDE 163 */ 164 #ifdef CONFIG_CMD_IDE 165 #define __io 166 #define CONFIG_IDE_PREINIT 167 #define CONFIG_DOS_PARTITION 168 #define CONFIG_CMD_EXT2 169 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 170 #define CONFIG_MVSATA_IDE 171 #define CONFIG_MVSATA_IDE_USE_PORT1 172 /* Needs byte-swapping for ATA data register */ 173 #define CONFIG_IDE_SWAP_IO 174 /* Data, registers and alternate blocks are at the same offset */ 175 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 176 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 177 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 178 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 179 #define CONFIG_SYS_ATA_STRIDE 4 180 /* Controller supports 48-bits LBA addressing */ 181 #define CONFIG_LBA48 182 /* A single bus, a single device */ 183 #define CONFIG_SYS_IDE_MAXBUS 1 184 #define CONFIG_SYS_IDE_MAXDEVICE 1 185 /* ATA registers base is at SATA controller base */ 186 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 187 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 188 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 189 /* end of IDE defines */ 190 #endif /* CMD_IDE */ 191 192 /* 193 * Common USB/EHCI configuration 194 */ 195 #ifdef CONFIG_CMD_USB 196 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 197 #define CONFIG_USB_EHCI_MARVELL 198 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 199 #define CONFIG_USB_STORAGE 200 #define CONFIG_DOS_PARTITION 201 #define CONFIG_ISO_PARTITION 202 #define CONFIG_SUPPORT_VFAT 203 #endif /* CONFIG_CMD_USB */ 204 205 /* 206 * I2C related stuff 207 */ 208 #ifdef CONFIG_CMD_I2C 209 #define CONFIG_SYS_I2C 210 #define CONFIG_SYS_I2C_MVTWSI 211 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 212 #define CONFIG_SYS_I2C_SLAVE 0x0 213 #define CONFIG_SYS_I2C_SPEED 100000 214 #endif 215 216 /* 217 * Environment variables configurations 218 */ 219 #define CONFIG_ENV_IS_IN_FLASH 1 220 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 221 #define CONFIG_ENV_SIZE 0x2000 222 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 223 224 /* 225 * Size of malloc() pool 226 */ 227 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 228 229 /* 230 * Other required minimal configurations 231 */ 232 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 233 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 234 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 235 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 236 #define CONFIG_NR_DRAM_BANKS 1 237 238 #define CONFIG_SYS_LOAD_ADDR 0x00800000 239 #define CONFIG_SYS_MEMTEST_START 0x00400000 240 #define CONFIG_SYS_MEMTEST_END 0x007fffff 241 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 242 #define CONFIG_SYS_MAXARGS 16 243 244 /* Use the HUSH parser */ 245 #define CONFIG_SYS_HUSH_PARSER 246 247 /* Enable command line editing */ 248 #define CONFIG_CMDLINE_EDITING 249 250 /* provide extensive help */ 251 #define CONFIG_SYS_LONGHELP 252 253 /* additions for new relocation code, must be added to all boards */ 254 #define CONFIG_SYS_SDRAM_BASE 0 255 #define CONFIG_SYS_INIT_SP_ADDR \ 256 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 257 258 #endif /* _CONFIG_EDMINIV2_H */ 259