1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_TEXT_BASE 0xffff0000 21 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 22 #define CONFIG_SPL_STACK 0x00020000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 25 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 27 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 28 #define CONFIG_SPL_BOARD_INIT 29 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 30 #define CONFIG_SYS_UBOOT_START 0x00800000 31 #define CONFIG_SYS_TEXT_BASE 0x00800000 32 33 /* 34 * Version number information 35 */ 36 37 #define CONFIG_IDENT_STRING " EDMiniV2" 38 39 /* 40 * High Level Configuration Options (easy to change) 41 */ 42 43 #define CONFIG_MARVELL 1 44 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 45 #define CONFIG_88F5182 1 /* SOC Name */ 46 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 47 48 #include <asm/arch/orion5x.h> 49 /* 50 * CLKs configurations 51 */ 52 53 /* 54 * Board-specific values for Orion5x MPP low level init: 55 * - MPPs 12 to 15 are SATA LEDs (mode 5) 56 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 57 * MPP16 to MPP19, mode 0 for others 58 */ 59 60 #define ORION5X_MPP0_7 0x00000003 61 #define ORION5X_MPP8_15 0x55550000 62 #define ORION5X_MPP16_23 0x00005555 63 64 /* 65 * Board-specific values for Orion5x GPIO low level init: 66 * - GPIO3 is input (RTC interrupt) 67 * - GPIO16 is Power LED control (0 = on, 1 = off) 68 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 69 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 70 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 71 * - GPIO22 is SATA disk power status () 72 * - GPIO23 is supply status for SATA disk () 73 * - GPIO24 is supply control for board (write 1 to power off) 74 * Last GPIO is 25, further bits are supposed to be 0. 75 * Enable mask has ones for INPUT, 0 for OUTPUT. 76 * Default is LED ON, board ON :) 77 */ 78 79 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 80 #define ORION5X_GPIO_OUT_VALUE 0x00000000 81 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 82 83 /* 84 * NS16550 Configuration 85 */ 86 87 #define CONFIG_SYS_NS16550_SERIAL 88 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 89 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 90 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 91 92 /* 93 * Serial Port configuration 94 * The following definitions let you select what serial you want to use 95 * for your console driver. 96 */ 97 98 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 99 #define CONFIG_BAUDRATE 115200 100 #define CONFIG_SYS_BAUDRATE_TABLE \ 101 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 102 103 /* 104 * FLASH configuration 105 */ 106 107 #define CONFIG_SYS_FLASH_CFI 108 #define CONFIG_FLASH_CFI_DRIVER 109 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 110 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 111 #define CONFIG_SYS_FLASH_BASE 0xfff80000 112 113 /* auto boot */ 114 115 /* 116 * For booting Linux, the board info and command line data 117 * have to be in the first 8 MB of memory, since this is 118 * the maximum mapped by the Linux kernel during initialization. 119 */ 120 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 121 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 122 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 123 124 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 125 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 126 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 127 /* 128 * Commands configuration 129 */ 130 #define CONFIG_CMD_IDE 131 132 /* 133 * Network 134 */ 135 136 #ifdef CONFIG_CMD_NET 137 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 138 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 139 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 140 #define CONFIG_PHY_BASE_ADR 0x8 141 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 142 #define CONFIG_NETCONSOLE /* include NetConsole support */ 143 #define CONFIG_MII /* expose smi ove miiphy interface */ 144 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 145 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 146 #endif 147 148 /* 149 * IDE 150 */ 151 #ifdef CONFIG_CMD_IDE 152 #define __io 153 #define CONFIG_IDE_PREINIT 154 #define CONFIG_DOS_PARTITION 155 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 156 #define CONFIG_MVSATA_IDE 157 #define CONFIG_MVSATA_IDE_USE_PORT1 158 /* Needs byte-swapping for ATA data register */ 159 #define CONFIG_IDE_SWAP_IO 160 /* Data, registers and alternate blocks are at the same offset */ 161 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 162 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 163 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 164 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 165 #define CONFIG_SYS_ATA_STRIDE 4 166 /* Controller supports 48-bits LBA addressing */ 167 #define CONFIG_LBA48 168 /* A single bus, a single device */ 169 #define CONFIG_SYS_IDE_MAXBUS 1 170 #define CONFIG_SYS_IDE_MAXDEVICE 1 171 /* ATA registers base is at SATA controller base */ 172 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 173 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 174 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 175 /* end of IDE defines */ 176 #endif /* CMD_IDE */ 177 178 /* 179 * Common USB/EHCI configuration 180 */ 181 #ifdef CONFIG_CMD_USB 182 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 183 #define CONFIG_USB_EHCI_MARVELL 184 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 185 #define CONFIG_DOS_PARTITION 186 #define CONFIG_ISO_PARTITION 187 #define CONFIG_SUPPORT_VFAT 188 #endif /* CONFIG_CMD_USB */ 189 190 /* 191 * I2C related stuff 192 */ 193 #ifdef CONFIG_CMD_I2C 194 #define CONFIG_SYS_I2C 195 #define CONFIG_SYS_I2C_MVTWSI 196 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 197 #define CONFIG_SYS_I2C_SLAVE 0x0 198 #define CONFIG_SYS_I2C_SPEED 100000 199 #endif 200 201 /* 202 * Environment variables configurations 203 */ 204 #define CONFIG_ENV_IS_IN_FLASH 1 205 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 206 #define CONFIG_ENV_SIZE 0x2000 207 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 208 209 /* 210 * Size of malloc() pool 211 */ 212 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 213 214 /* 215 * Other required minimal configurations 216 */ 217 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 218 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 219 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 220 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 221 #define CONFIG_NR_DRAM_BANKS 1 222 223 #define CONFIG_SYS_LOAD_ADDR 0x00800000 224 #define CONFIG_SYS_MEMTEST_START 0x00400000 225 #define CONFIG_SYS_MEMTEST_END 0x007fffff 226 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 227 #define CONFIG_SYS_MAXARGS 16 228 229 /* Enable command line editing */ 230 #define CONFIG_CMDLINE_EDITING 231 232 /* provide extensive help */ 233 #define CONFIG_SYS_LONGHELP 234 235 /* additions for new relocation code, must be added to all boards */ 236 #define CONFIG_SYS_SDRAM_BASE 0 237 #define CONFIG_SYS_INIT_SP_ADDR \ 238 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 239 240 #endif /* _CONFIG_EDMINIV2_H */ 241