1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * Version number information 17 */ 18 19 #define CONFIG_IDENT_STRING " EDMiniV2" 20 21 /* 22 * High Level Configuration Options (easy to change) 23 */ 24 25 #define CONFIG_MARVELL 1 26 #define CONFIG_ARM926EJS 1 /* Basic Architecture */ 27 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 28 #define CONFIG_ORION5X 1 /* SOC Family Name */ 29 #define CONFIG_88F5182 1 /* SOC Name */ 30 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 31 32 #include <asm/arch/orion5x.h> 33 /* 34 * CLKs configurations 35 */ 36 37 /* 38 * Board-specific values for Orion5x MPP low level init: 39 * - MPPs 12 to 15 are SATA LEDs (mode 5) 40 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 41 * MPP16 to MPP19, mode 0 for others 42 */ 43 44 #define ORION5X_MPP0_7 0x00000003 45 #define ORION5X_MPP8_15 0x55550000 46 #define ORION5X_MPP16_23 0x00005555 47 48 /* 49 * Board-specific values for Orion5x GPIO low level init: 50 * - GPIO3 is input (RTC interrupt) 51 * - GPIO16 is Power LED control (0 = on, 1 = off) 52 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 53 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 54 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 55 * - GPIO22 is SATA disk power status () 56 * - GPIO23 is supply status for SATA disk () 57 * - GPIO24 is supply control for board (write 1 to power off) 58 * Last GPIO is 25, further bits are supposed to be 0. 59 * Enable mask has ones for INPUT, 0 for OUTPUT. 60 * Default is LED ON, board ON :) 61 */ 62 63 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 64 #define ORION5X_GPIO_OUT_VALUE 0x00000000 65 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 66 67 /* 68 * NS16550 Configuration 69 */ 70 71 #define CONFIG_SYS_NS16550 72 #define CONFIG_SYS_NS16550_SERIAL 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 74 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 75 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 76 77 /* 78 * Serial Port configuration 79 * The following definitions let you select what serial you want to use 80 * for your console driver. 81 */ 82 83 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 84 #define CONFIG_BAUDRATE 115200 85 #define CONFIG_SYS_BAUDRATE_TABLE \ 86 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 87 88 /* 89 * FLASH configuration 90 */ 91 92 #define CONFIG_SYS_FLASH_CFI 93 #define CONFIG_FLASH_CFI_DRIVER 94 #define CONFIG_FLASH_CFI_LEGACY 95 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 96 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 97 #define CONFIG_SYS_FLASH_BASE 0xfff80000 98 #define CONFIG_SYS_FLASH_SECTSZ \ 99 {16384, 8192, 8192, 32768, \ 100 65536, 65536, 65536, 65536, 65536, 65536, 65536} 101 102 /* auto boot */ 103 #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ 104 105 /* 106 * For booting Linux, the board info and command line data 107 * have to be in the first 8 MB of memory, since this is 108 * the maximum mapped by the Linux kernel during initialization. 109 */ 110 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 111 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 112 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 113 114 #define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ 115 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 116 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 117 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 118 /* 119 * Commands configuration - using default command set for now 120 */ 121 #include <config_cmd_default.h> 122 #define CONFIG_CMD_IDE 123 #define CONFIG_CMD_I2C 124 #define CONFIG_CMD_USB 125 126 /* 127 * Network 128 */ 129 130 #ifdef CONFIG_CMD_NET 131 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 132 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 133 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 134 #define CONFIG_PHY_BASE_ADR 0x8 135 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 136 #define CONFIG_NETCONSOLE /* include NetConsole support */ 137 #define CONFIG_MII /* expose smi ove miiphy interface */ 138 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 139 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 140 #endif 141 142 /* 143 * IDE 144 */ 145 #ifdef CONFIG_CMD_IDE 146 #define __io 147 #define CONFIG_IDE_PREINIT 148 #define CONFIG_DOS_PARTITION 149 #define CONFIG_CMD_EXT2 150 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 151 #define CONFIG_MVSATA_IDE 152 #define CONFIG_MVSATA_IDE_USE_PORT1 153 /* Needs byte-swapping for ATA data register */ 154 #define CONFIG_IDE_SWAP_IO 155 /* Data, registers and alternate blocks are at the same offset */ 156 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 157 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 158 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 159 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 160 #define CONFIG_SYS_ATA_STRIDE 4 161 /* Controller supports 48-bits LBA addressing */ 162 #define CONFIG_LBA48 163 /* A single bus, a single device */ 164 #define CONFIG_SYS_IDE_MAXBUS 1 165 #define CONFIG_SYS_IDE_MAXDEVICE 1 166 /* ATA registers base is at SATA controller base */ 167 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 168 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 169 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 170 /* end of IDE defines */ 171 #endif /* CMD_IDE */ 172 173 /* 174 * Common USB/EHCI configuration 175 */ 176 #ifdef CONFIG_CMD_USB 177 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 178 #define CONFIG_USB_EHCI_MARVELL 179 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 180 #define CONFIG_USB_STORAGE 181 #define CONFIG_DOS_PARTITION 182 #define CONFIG_ISO_PARTITION 183 #define CONFIG_SUPPORT_VFAT 184 #endif /* CONFIG_CMD_USB */ 185 186 /* 187 * I2C related stuff 188 */ 189 #ifdef CONFIG_CMD_I2C 190 #define CONFIG_I2C_MVTWSI 191 #define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE 192 #define CONFIG_SYS_I2C_SLAVE 0x0 193 #define CONFIG_SYS_I2C_SPEED 100000 194 #endif 195 196 /* 197 * Environment variables configurations 198 */ 199 #define CONFIG_ENV_IS_IN_FLASH 1 200 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 201 #define CONFIG_ENV_SIZE 0x2000 202 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 203 204 /* 205 * Size of malloc() pool 206 */ 207 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 208 209 /* 210 * Other required minimal configurations 211 */ 212 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 213 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 214 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 215 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 216 #define CONFIG_NR_DRAM_BANKS 1 217 218 #define CONFIG_SYS_LOAD_ADDR 0x00800000 219 #define CONFIG_SYS_MEMTEST_START 0x00400000 220 #define CONFIG_SYS_MEMTEST_END 0x007fffff 221 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 222 #define CONFIG_SYS_MAXARGS 16 223 224 /* Use the HUSH parser */ 225 #define CONFIG_SYS_HUSH_PARSER 226 227 /* Enable command line editing */ 228 #define CONFIG_CMDLINE_EDITING 229 230 /* provide extensive help */ 231 #define CONFIG_SYS_LONGHELP 232 233 /* additions for new relocation code, must be added to all boards */ 234 #define CONFIG_SYS_SDRAM_BASE 0 235 #define CONFIG_SYS_INIT_SP_ADDR \ 236 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 237 238 #endif /* _CONFIG_EDMINIV2_H */ 239