1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * Version number information 17 */ 18 19 #define CONFIG_IDENT_STRING " EDMiniV2" 20 21 /* 22 * High Level Configuration Options (easy to change) 23 */ 24 25 #define CONFIG_MARVELL 1 26 #define CONFIG_ARM926EJS 1 /* Basic Architecture */ 27 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 28 #define CONFIG_ORION5X 1 /* SOC Family Name */ 29 #define CONFIG_88F5182 1 /* SOC Name */ 30 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 31 32 #include <asm/arch/orion5x.h> 33 /* 34 * CLKs configurations 35 */ 36 37 #define CONFIG_SYS_HZ 1000 38 39 /* 40 * Board-specific values for Orion5x MPP low level init: 41 * - MPPs 12 to 15 are SATA LEDs (mode 5) 42 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 43 * MPP16 to MPP19, mode 0 for others 44 */ 45 46 #define ORION5X_MPP0_7 0x00000003 47 #define ORION5X_MPP8_15 0x55550000 48 #define ORION5X_MPP16_23 0x00005555 49 50 /* 51 * Board-specific values for Orion5x GPIO low level init: 52 * - GPIO3 is input (RTC interrupt) 53 * - GPIO16 is Power LED control (0 = on, 1 = off) 54 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 55 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 56 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 57 * - GPIO22 is SATA disk power status () 58 * - GPIO23 is supply status for SATA disk () 59 * - GPIO24 is supply control for board (write 1 to power off) 60 * Last GPIO is 25, further bits are supposed to be 0. 61 * Enable mask has ones for INPUT, 0 for OUTPUT. 62 * Default is LED ON, board ON :) 63 */ 64 65 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 66 #define ORION5X_GPIO_OUT_VALUE 0x00000000 67 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 68 69 /* 70 * NS16550 Configuration 71 */ 72 73 #define CONFIG_SYS_NS16550 74 #define CONFIG_SYS_NS16550_SERIAL 75 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 76 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 77 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 78 79 /* 80 * Serial Port configuration 81 * The following definitions let you select what serial you want to use 82 * for your console driver. 83 */ 84 85 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE \ 88 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 89 90 /* 91 * FLASH configuration 92 */ 93 94 #define CONFIG_SYS_FLASH_CFI 95 #define CONFIG_FLASH_CFI_DRIVER 96 #define CONFIG_FLASH_CFI_LEGACY 97 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 98 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 99 #define CONFIG_SYS_FLASH_BASE 0xfff80000 100 #define CONFIG_SYS_FLASH_SECTSZ \ 101 {16384, 8192, 8192, 32768, \ 102 65536, 65536, 65536, 65536, 65536, 65536, 65536} 103 104 /* auto boot */ 105 #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ 106 107 /* 108 * For booting Linux, the board info and command line data 109 * have to be in the first 8 MB of memory, since this is 110 * the maximum mapped by the Linux kernel during initialization. 111 */ 112 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 113 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 114 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 115 116 #define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */ 117 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 119 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 120 /* 121 * Commands configuration - using default command set for now 122 */ 123 #include <config_cmd_default.h> 124 #define CONFIG_CMD_IDE 125 #define CONFIG_CMD_I2C 126 #define CONFIG_CMD_USB 127 128 /* 129 * Network 130 */ 131 132 #ifdef CONFIG_CMD_NET 133 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 134 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 135 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 136 #define CONFIG_PHY_BASE_ADR 0x8 137 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 138 #define CONFIG_NETCONSOLE /* include NetConsole support */ 139 #define CONFIG_MII /* expose smi ove miiphy interface */ 140 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 141 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 142 #endif 143 144 /* 145 * IDE 146 */ 147 #ifdef CONFIG_CMD_IDE 148 #define __io 149 #define CONFIG_IDE_PREINIT 150 #define CONFIG_DOS_PARTITION 151 #define CONFIG_CMD_EXT2 152 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 153 #define CONFIG_MVSATA_IDE 154 #define CONFIG_MVSATA_IDE_USE_PORT1 155 /* Needs byte-swapping for ATA data register */ 156 #define CONFIG_IDE_SWAP_IO 157 /* Data, registers and alternate blocks are at the same offset */ 158 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 159 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 160 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 161 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 162 #define CONFIG_SYS_ATA_STRIDE 4 163 /* Controller supports 48-bits LBA addressing */ 164 #define CONFIG_LBA48 165 /* A single bus, a single device */ 166 #define CONFIG_SYS_IDE_MAXBUS 1 167 #define CONFIG_SYS_IDE_MAXDEVICE 1 168 /* ATA registers base is at SATA controller base */ 169 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 170 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 171 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 172 /* end of IDE defines */ 173 #endif /* CMD_IDE */ 174 175 /* 176 * Common USB/EHCI configuration 177 */ 178 #ifdef CONFIG_CMD_USB 179 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 180 #define CONFIG_USB_EHCI_MARVELL 181 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 182 #define CONFIG_USB_STORAGE 183 #define CONFIG_DOS_PARTITION 184 #define CONFIG_ISO_PARTITION 185 #define CONFIG_SUPPORT_VFAT 186 #endif /* CONFIG_CMD_USB */ 187 188 /* 189 * I2C related stuff 190 */ 191 #ifdef CONFIG_CMD_I2C 192 #define CONFIG_I2C_MVTWSI 193 #define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE 194 #define CONFIG_SYS_I2C_SLAVE 0x0 195 #define CONFIG_SYS_I2C_SPEED 100000 196 #endif 197 198 /* 199 * Environment variables configurations 200 */ 201 #define CONFIG_ENV_IS_IN_FLASH 1 202 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 203 #define CONFIG_ENV_SIZE 0x2000 204 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 205 206 /* 207 * Size of malloc() pool 208 */ 209 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 210 211 /* 212 * Other required minimal configurations 213 */ 214 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 215 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 216 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 217 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 218 #define CONFIG_NR_DRAM_BANKS 1 219 220 #define CONFIG_SYS_LOAD_ADDR 0x00800000 221 #define CONFIG_SYS_MEMTEST_START 0x00400000 222 #define CONFIG_SYS_MEMTEST_END 0x007fffff 223 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 224 #define CONFIG_SYS_MAXARGS 16 225 226 /* Use the HUSH parser */ 227 #define CONFIG_SYS_HUSH_PARSER 228 229 /* Enable command line editing */ 230 #define CONFIG_CMDLINE_EDITING 231 232 /* provide extensive help */ 233 #define CONFIG_SYS_LONGHELP 234 235 /* additions for new relocation code, must be added to all boards */ 236 #define CONFIG_SYS_SDRAM_BASE 0 237 #define CONFIG_SYS_INIT_SP_ADDR \ 238 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 239 240 #endif /* _CONFIG_EDMINIV2_H */ 241