1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_TEXT_BASE 0xffff0000 21 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 22 #define CONFIG_SPL_STACK 0x00020000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 25 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 27 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 28 #define CONFIG_SPL_BOARD_INIT 29 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 30 #define CONFIG_SYS_UBOOT_START 0x00800000 31 #define CONFIG_SYS_TEXT_BASE 0x00800000 32 33 /* 34 * High Level Configuration Options (easy to change) 35 */ 36 37 #define CONFIG_MARVELL 1 38 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 39 #define CONFIG_88F5182 1 /* SOC Name */ 40 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 41 42 #include <asm/arch/orion5x.h> 43 /* 44 * CLKs configurations 45 */ 46 47 /* 48 * Board-specific values for Orion5x MPP low level init: 49 * - MPPs 12 to 15 are SATA LEDs (mode 5) 50 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 51 * MPP16 to MPP19, mode 0 for others 52 */ 53 54 #define ORION5X_MPP0_7 0x00000003 55 #define ORION5X_MPP8_15 0x55550000 56 #define ORION5X_MPP16_23 0x00005555 57 58 /* 59 * Board-specific values for Orion5x GPIO low level init: 60 * - GPIO3 is input (RTC interrupt) 61 * - GPIO16 is Power LED control (0 = on, 1 = off) 62 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 63 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 64 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 65 * - GPIO22 is SATA disk power status () 66 * - GPIO23 is supply status for SATA disk () 67 * - GPIO24 is supply control for board (write 1 to power off) 68 * Last GPIO is 25, further bits are supposed to be 0. 69 * Enable mask has ones for INPUT, 0 for OUTPUT. 70 * Default is LED ON, board ON :) 71 */ 72 73 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 74 #define ORION5X_GPIO_OUT_VALUE 0x00000000 75 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 76 77 /* 78 * NS16550 Configuration 79 */ 80 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 83 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 84 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 85 86 /* 87 * Serial Port configuration 88 * The following definitions let you select what serial you want to use 89 * for your console driver. 90 */ 91 92 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 93 #define CONFIG_SYS_BAUDRATE_TABLE \ 94 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 95 96 /* 97 * FLASH configuration 98 */ 99 100 #define CONFIG_SYS_FLASH_CFI 101 #define CONFIG_FLASH_CFI_DRIVER 102 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 103 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 104 #define CONFIG_SYS_FLASH_BASE 0xfff80000 105 106 /* auto boot */ 107 108 /* 109 * For booting Linux, the board info and command line data 110 * have to be in the first 8 MB of memory, since this is 111 * the maximum mapped by the Linux kernel during initialization. 112 */ 113 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 114 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 115 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 116 117 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 119 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 120 /* 121 * Commands configuration 122 */ 123 #define CONFIG_CMD_IDE 124 125 /* 126 * Network 127 */ 128 129 #ifdef CONFIG_CMD_NET 130 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 131 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 132 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 133 #define CONFIG_PHY_BASE_ADR 0x8 134 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 135 #define CONFIG_NETCONSOLE /* include NetConsole support */ 136 #define CONFIG_MII /* expose smi ove miiphy interface */ 137 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 138 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 139 #endif 140 141 /* 142 * IDE 143 */ 144 #ifdef CONFIG_CMD_IDE 145 #define __io 146 #define CONFIG_IDE_PREINIT 147 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 148 #define CONFIG_MVSATA_IDE 149 #define CONFIG_MVSATA_IDE_USE_PORT1 150 /* Needs byte-swapping for ATA data register */ 151 #define CONFIG_IDE_SWAP_IO 152 /* Data, registers and alternate blocks are at the same offset */ 153 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 154 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 155 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 156 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 157 #define CONFIG_SYS_ATA_STRIDE 4 158 /* Controller supports 48-bits LBA addressing */ 159 #define CONFIG_LBA48 160 /* A single bus, a single device */ 161 #define CONFIG_SYS_IDE_MAXBUS 1 162 #define CONFIG_SYS_IDE_MAXDEVICE 1 163 /* ATA registers base is at SATA controller base */ 164 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 165 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 166 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 167 /* end of IDE defines */ 168 #endif /* CMD_IDE */ 169 170 /* 171 * Common USB/EHCI configuration 172 */ 173 #ifdef CONFIG_CMD_USB 174 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 175 #define CONFIG_USB_EHCI_MARVELL 176 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 177 #define CONFIG_SUPPORT_VFAT 178 #endif /* CONFIG_CMD_USB */ 179 180 /* 181 * I2C related stuff 182 */ 183 #ifdef CONFIG_CMD_I2C 184 #define CONFIG_SYS_I2C 185 #define CONFIG_SYS_I2C_MVTWSI 186 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 187 #define CONFIG_SYS_I2C_SLAVE 0x0 188 #define CONFIG_SYS_I2C_SPEED 100000 189 #endif 190 191 /* 192 * Environment variables configurations 193 */ 194 #define CONFIG_ENV_IS_IN_FLASH 1 195 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 196 #define CONFIG_ENV_SIZE 0x2000 197 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 198 199 /* 200 * Size of malloc() pool 201 */ 202 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 203 204 /* 205 * Other required minimal configurations 206 */ 207 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 208 #define CONFIG_NR_DRAM_BANKS 1 209 210 #define CONFIG_SYS_LOAD_ADDR 0x00800000 211 #define CONFIG_SYS_MEMTEST_START 0x00400000 212 #define CONFIG_SYS_MEMTEST_END 0x007fffff 213 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 214 #define CONFIG_SYS_MAXARGS 16 215 216 /* Enable command line editing */ 217 #define CONFIG_CMDLINE_EDITING 218 219 /* provide extensive help */ 220 #define CONFIG_SYS_LONGHELP 221 222 /* additions for new relocation code, must be added to all boards */ 223 #define CONFIG_SYS_SDRAM_BASE 0 224 #define CONFIG_SYS_INIT_SP_ADDR \ 225 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 226 227 #endif /* _CONFIG_EDMINIV2_H */ 228