1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_TEXT_BASE 0xffff0000 21 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 22 #define CONFIG_SPL_STACK 0x00020000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 25 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 27 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 28 #define CONFIG_SPL_BOARD_INIT 29 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 30 #define CONFIG_SYS_UBOOT_START 0x00800000 31 #define CONFIG_SYS_TEXT_BASE 0x00800000 32 33 /* 34 * High Level Configuration Options (easy to change) 35 */ 36 37 #define CONFIG_MARVELL 1 38 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 39 #define CONFIG_88F5182 1 /* SOC Name */ 40 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 41 42 #include <asm/arch/orion5x.h> 43 /* 44 * CLKs configurations 45 */ 46 47 /* 48 * Board-specific values for Orion5x MPP low level init: 49 * - MPPs 12 to 15 are SATA LEDs (mode 5) 50 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 51 * MPP16 to MPP19, mode 0 for others 52 */ 53 54 #define ORION5X_MPP0_7 0x00000003 55 #define ORION5X_MPP8_15 0x55550000 56 #define ORION5X_MPP16_23 0x00005555 57 58 /* 59 * Board-specific values for Orion5x GPIO low level init: 60 * - GPIO3 is input (RTC interrupt) 61 * - GPIO16 is Power LED control (0 = on, 1 = off) 62 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 63 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 64 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 65 * - GPIO22 is SATA disk power status () 66 * - GPIO23 is supply status for SATA disk () 67 * - GPIO24 is supply control for board (write 1 to power off) 68 * Last GPIO is 25, further bits are supposed to be 0. 69 * Enable mask has ones for INPUT, 0 for OUTPUT. 70 * Default is LED ON, board ON :) 71 */ 72 73 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 74 #define ORION5X_GPIO_OUT_VALUE 0x00000000 75 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 76 77 /* 78 * NS16550 Configuration 79 */ 80 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 83 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 84 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 85 86 /* 87 * Serial Port configuration 88 * The following definitions let you select what serial you want to use 89 * for your console driver. 90 */ 91 92 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 93 #define CONFIG_BAUDRATE 115200 94 #define CONFIG_SYS_BAUDRATE_TABLE \ 95 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 96 97 /* 98 * FLASH configuration 99 */ 100 101 #define CONFIG_SYS_FLASH_CFI 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 104 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 105 #define CONFIG_SYS_FLASH_BASE 0xfff80000 106 107 /* auto boot */ 108 109 /* 110 * For booting Linux, the board info and command line data 111 * have to be in the first 8 MB of memory, since this is 112 * the maximum mapped by the Linux kernel during initialization. 113 */ 114 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 115 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 116 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 117 118 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 120 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 121 /* 122 * Commands configuration 123 */ 124 #define CONFIG_CMD_IDE 125 126 /* 127 * Network 128 */ 129 130 #ifdef CONFIG_CMD_NET 131 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 132 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 133 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 134 #define CONFIG_PHY_BASE_ADR 0x8 135 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 136 #define CONFIG_NETCONSOLE /* include NetConsole support */ 137 #define CONFIG_MII /* expose smi ove miiphy interface */ 138 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 139 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 140 #endif 141 142 /* 143 * IDE 144 */ 145 #ifdef CONFIG_CMD_IDE 146 #define __io 147 #define CONFIG_IDE_PREINIT 148 #define CONFIG_DOS_PARTITION 149 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 150 #define CONFIG_MVSATA_IDE 151 #define CONFIG_MVSATA_IDE_USE_PORT1 152 /* Needs byte-swapping for ATA data register */ 153 #define CONFIG_IDE_SWAP_IO 154 /* Data, registers and alternate blocks are at the same offset */ 155 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 156 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 157 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 158 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 159 #define CONFIG_SYS_ATA_STRIDE 4 160 /* Controller supports 48-bits LBA addressing */ 161 #define CONFIG_LBA48 162 /* A single bus, a single device */ 163 #define CONFIG_SYS_IDE_MAXBUS 1 164 #define CONFIG_SYS_IDE_MAXDEVICE 1 165 /* ATA registers base is at SATA controller base */ 166 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 167 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 168 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 169 /* end of IDE defines */ 170 #endif /* CMD_IDE */ 171 172 /* 173 * Common USB/EHCI configuration 174 */ 175 #ifdef CONFIG_CMD_USB 176 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 177 #define CONFIG_USB_EHCI_MARVELL 178 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 179 #define CONFIG_DOS_PARTITION 180 #define CONFIG_ISO_PARTITION 181 #define CONFIG_SUPPORT_VFAT 182 #endif /* CONFIG_CMD_USB */ 183 184 /* 185 * I2C related stuff 186 */ 187 #ifdef CONFIG_CMD_I2C 188 #define CONFIG_SYS_I2C 189 #define CONFIG_SYS_I2C_MVTWSI 190 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 191 #define CONFIG_SYS_I2C_SLAVE 0x0 192 #define CONFIG_SYS_I2C_SPEED 100000 193 #endif 194 195 /* 196 * Environment variables configurations 197 */ 198 #define CONFIG_ENV_IS_IN_FLASH 1 199 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 200 #define CONFIG_ENV_SIZE 0x2000 201 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 202 203 /* 204 * Size of malloc() pool 205 */ 206 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 207 208 /* 209 * Other required minimal configurations 210 */ 211 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 212 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 213 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 214 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 215 #define CONFIG_NR_DRAM_BANKS 1 216 217 #define CONFIG_SYS_LOAD_ADDR 0x00800000 218 #define CONFIG_SYS_MEMTEST_START 0x00400000 219 #define CONFIG_SYS_MEMTEST_END 0x007fffff 220 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 221 #define CONFIG_SYS_MAXARGS 16 222 223 /* Enable command line editing */ 224 #define CONFIG_CMDLINE_EDITING 225 226 /* provide extensive help */ 227 #define CONFIG_SYS_LONGHELP 228 229 /* additions for new relocation code, must be added to all boards */ 230 #define CONFIG_SYS_SDRAM_BASE 0 231 #define CONFIG_SYS_INIT_SP_ADDR \ 232 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 233 234 #endif /* _CONFIG_EDMINIV2_H */ 235