1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_LIBGENERIC_SUPPORT 21 #define CONFIG_SPL_LIBCOMMON_SUPPORT 22 #define CONFIG_SPL_SERIAL_SUPPORT 23 #define CONFIG_SPL_NOR_SUPPORT 24 #define CONFIG_SPL_TEXT_BASE 0xffff0000 25 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 26 #define CONFIG_SPL_STACK 0x00020000 27 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 28 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 29 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 30 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 31 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" 32 #define CONFIG_SPL_BOARD_INIT 33 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 34 #define CONFIG_SYS_UBOOT_START 0x00800000 35 #define CONFIG_SYS_TEXT_BASE 0x00800000 36 37 /* 38 * Version number information 39 */ 40 41 #define CONFIG_IDENT_STRING " EDMiniV2" 42 43 /* 44 * High Level Configuration Options (easy to change) 45 */ 46 47 #define CONFIG_MARVELL 1 48 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 49 #define CONFIG_88F5182 1 /* SOC Name */ 50 #define CONFIG_MACH_EDMINIV2 1 /* Machine type */ 51 52 #include <asm/arch/orion5x.h> 53 /* 54 * CLKs configurations 55 */ 56 57 /* 58 * Board-specific values for Orion5x MPP low level init: 59 * - MPPs 12 to 15 are SATA LEDs (mode 5) 60 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 61 * MPP16 to MPP19, mode 0 for others 62 */ 63 64 #define ORION5X_MPP0_7 0x00000003 65 #define ORION5X_MPP8_15 0x55550000 66 #define ORION5X_MPP16_23 0x00005555 67 68 /* 69 * Board-specific values for Orion5x GPIO low level init: 70 * - GPIO3 is input (RTC interrupt) 71 * - GPIO16 is Power LED control (0 = on, 1 = off) 72 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 73 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 74 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 75 * - GPIO22 is SATA disk power status () 76 * - GPIO23 is supply status for SATA disk () 77 * - GPIO24 is supply control for board (write 1 to power off) 78 * Last GPIO is 25, further bits are supposed to be 0. 79 * Enable mask has ones for INPUT, 0 for OUTPUT. 80 * Default is LED ON, board ON :) 81 */ 82 83 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 84 #define ORION5X_GPIO_OUT_VALUE 0x00000000 85 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 86 87 /* 88 * NS16550 Configuration 89 */ 90 91 #define CONFIG_SYS_NS16550_SERIAL 92 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 93 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 94 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 95 96 /* 97 * Serial Port configuration 98 * The following definitions let you select what serial you want to use 99 * for your console driver. 100 */ 101 102 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 103 #define CONFIG_BAUDRATE 115200 104 #define CONFIG_SYS_BAUDRATE_TABLE \ 105 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 106 107 /* 108 * FLASH configuration 109 */ 110 111 #define CONFIG_SYS_FLASH_CFI 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 114 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 115 #define CONFIG_SYS_FLASH_BASE 0xfff80000 116 117 /* auto boot */ 118 #define CONFIG_BOOTDELAY 3 /* default enable autoboot */ 119 120 /* 121 * For booting Linux, the board info and command line data 122 * have to be in the first 8 MB of memory, since this is 123 * the maximum mapped by the Linux kernel during initialization. 124 */ 125 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 126 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 127 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 128 129 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 131 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ 132 /* 133 * Commands configuration 134 */ 135 #define CONFIG_CMD_IDE 136 #define CONFIG_CMD_I2C 137 #define CONFIG_CMD_USB 138 139 /* 140 * Network 141 */ 142 143 #ifdef CONFIG_CMD_NET 144 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 145 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 146 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 147 #define CONFIG_PHY_BASE_ADR 0x8 148 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 149 #define CONFIG_NETCONSOLE /* include NetConsole support */ 150 #define CONFIG_MII /* expose smi ove miiphy interface */ 151 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 152 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 153 #endif 154 155 /* 156 * IDE 157 */ 158 #ifdef CONFIG_CMD_IDE 159 #define __io 160 #define CONFIG_IDE_PREINIT 161 #define CONFIG_DOS_PARTITION 162 #define CONFIG_CMD_EXT2 163 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 164 #define CONFIG_MVSATA_IDE 165 #define CONFIG_MVSATA_IDE_USE_PORT1 166 /* Needs byte-swapping for ATA data register */ 167 #define CONFIG_IDE_SWAP_IO 168 /* Data, registers and alternate blocks are at the same offset */ 169 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 170 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 171 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 172 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 173 #define CONFIG_SYS_ATA_STRIDE 4 174 /* Controller supports 48-bits LBA addressing */ 175 #define CONFIG_LBA48 176 /* A single bus, a single device */ 177 #define CONFIG_SYS_IDE_MAXBUS 1 178 #define CONFIG_SYS_IDE_MAXDEVICE 1 179 /* ATA registers base is at SATA controller base */ 180 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 181 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 182 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 183 /* end of IDE defines */ 184 #endif /* CMD_IDE */ 185 186 /* 187 * Common USB/EHCI configuration 188 */ 189 #ifdef CONFIG_CMD_USB 190 #define CONFIG_USB_EHCI /* Enable EHCI USB support */ 191 #define CONFIG_USB_EHCI_MARVELL 192 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 193 #define CONFIG_USB_STORAGE 194 #define CONFIG_DOS_PARTITION 195 #define CONFIG_ISO_PARTITION 196 #define CONFIG_SUPPORT_VFAT 197 #endif /* CONFIG_CMD_USB */ 198 199 /* 200 * I2C related stuff 201 */ 202 #ifdef CONFIG_CMD_I2C 203 #define CONFIG_SYS_I2C 204 #define CONFIG_SYS_I2C_MVTWSI 205 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 206 #define CONFIG_SYS_I2C_SLAVE 0x0 207 #define CONFIG_SYS_I2C_SPEED 100000 208 #endif 209 210 /* 211 * Environment variables configurations 212 */ 213 #define CONFIG_ENV_IS_IN_FLASH 1 214 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 215 #define CONFIG_ENV_SIZE 0x2000 216 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 217 218 /* 219 * Size of malloc() pool 220 */ 221 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 222 223 /* 224 * Other required minimal configurations 225 */ 226 #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ 227 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 228 #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ 229 #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ 230 #define CONFIG_NR_DRAM_BANKS 1 231 232 #define CONFIG_SYS_LOAD_ADDR 0x00800000 233 #define CONFIG_SYS_MEMTEST_START 0x00400000 234 #define CONFIG_SYS_MEMTEST_END 0x007fffff 235 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 236 #define CONFIG_SYS_MAXARGS 16 237 238 /* Use the HUSH parser */ 239 #define CONFIG_SYS_HUSH_PARSER 240 241 /* Enable command line editing */ 242 #define CONFIG_CMDLINE_EDITING 243 244 /* provide extensive help */ 245 #define CONFIG_SYS_LONGHELP 246 247 /* additions for new relocation code, must be added to all boards */ 248 #define CONFIG_SYS_SDRAM_BASE 0 249 #define CONFIG_SYS_INIT_SP_ADDR \ 250 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 251 252 #endif /* _CONFIG_EDMINIV2_H */ 253