1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirkwood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _CONFIG_EDMINIV2_H 13 #define _CONFIG_EDMINIV2_H 14 15 /* 16 * SPL 17 */ 18 19 #define CONFIG_SPL_FRAMEWORK 20 #define CONFIG_SPL_TEXT_BASE 0xffff0000 21 #define CONFIG_SPL_MAX_SIZE 0x0000fff0 22 #define CONFIG_SPL_STACK 0x00020000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00020000 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff 25 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff 27 #define CONFIG_SYS_UBOOT_BASE 0xfff90000 28 #define CONFIG_SYS_UBOOT_START 0x00800000 29 #define CONFIG_SYS_TEXT_BASE 0x00800000 30 31 /* 32 * High Level Configuration Options (easy to change) 33 */ 34 35 #define CONFIG_MARVELL 1 36 #define CONFIG_FEROCEON 1 /* CPU Core subversion */ 37 #define CONFIG_88F5182 1 /* SOC Name */ 38 39 #include <asm/arch/orion5x.h> 40 /* 41 * CLKs configurations 42 */ 43 44 /* 45 * Board-specific values for Orion5x MPP low level init: 46 * - MPPs 12 to 15 are SATA LEDs (mode 5) 47 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for 48 * MPP16 to MPP19, mode 0 for others 49 */ 50 51 #define ORION5X_MPP0_7 0x00000003 52 #define ORION5X_MPP8_15 0x55550000 53 #define ORION5X_MPP16_23 0x00005555 54 55 /* 56 * Board-specific values for Orion5x GPIO low level init: 57 * - GPIO3 is input (RTC interrupt) 58 * - GPIO16 is Power LED control (0 = on, 1 = off) 59 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) 60 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) 61 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) 62 * - GPIO22 is SATA disk power status () 63 * - GPIO23 is supply status for SATA disk () 64 * - GPIO24 is supply control for board (write 1 to power off) 65 * Last GPIO is 25, further bits are supposed to be 0. 66 * Enable mask has ones for INPUT, 0 for OUTPUT. 67 * Default is LED ON, board ON :) 68 */ 69 70 #define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca 71 #define ORION5X_GPIO_OUT_VALUE 0x00000000 72 #define ORION5X_GPIO_IN_POLARITY 0x000000d0 73 74 /* 75 * NS16550 Configuration 76 */ 77 78 #define CONFIG_SYS_NS16550_SERIAL 79 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 81 #define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE 82 83 /* 84 * Serial Port configuration 85 * The following definitions let you select what serial you want to use 86 * for your console driver. 87 */ 88 89 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 90 #define CONFIG_SYS_BAUDRATE_TABLE \ 91 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } 92 93 /* 94 * FLASH configuration 95 */ 96 97 #define CONFIG_SYS_FLASH_CFI 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 100 #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ 101 #define CONFIG_SYS_FLASH_BASE 0xfff80000 102 103 /* auto boot */ 104 105 /* 106 * For booting Linux, the board info and command line data 107 * have to be in the first 8 MB of memory, since this is 108 * the maximum mapped by the Linux kernel during initialization. 109 */ 110 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 111 #define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ 112 #define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ 113 114 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 115 /* 116 * Commands configuration 117 */ 118 119 /* 120 * Network 121 */ 122 123 #ifdef CONFIG_CMD_NET 124 #define CONFIG_MVGBE /* Enable Marvell GbE Driver */ 125 #define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ 126 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ 127 #define CONFIG_PHY_BASE_ADR 0x8 128 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ 129 #define CONFIG_NETCONSOLE /* include NetConsole support */ 130 #define CONFIG_MII /* expose smi ove miiphy interface */ 131 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ 132 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 133 #endif 134 135 /* 136 * IDE 137 */ 138 #ifdef CONFIG_IDE 139 #define __io 140 #define CONFIG_IDE_PREINIT 141 /* ED Mini V has an IDE-compatible SATA connector for port 1 */ 142 #define CONFIG_MVSATA_IDE_USE_PORT1 143 /* Needs byte-swapping for ATA data register */ 144 #define CONFIG_IDE_SWAP_IO 145 /* Data, registers and alternate blocks are at the same offset */ 146 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) 147 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100) 148 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) 149 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 150 #define CONFIG_SYS_ATA_STRIDE 4 151 /* Controller supports 48-bits LBA addressing */ 152 #define CONFIG_LBA48 153 /* A single bus, a single device */ 154 #define CONFIG_SYS_IDE_MAXBUS 1 155 #define CONFIG_SYS_IDE_MAXDEVICE 1 156 /* ATA registers base is at SATA controller base */ 157 #define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE 158 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */ 159 #define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET 160 /* end of IDE defines */ 161 #endif /* CMD_IDE */ 162 163 /* 164 * Common USB/EHCI configuration 165 */ 166 #ifdef CONFIG_CMD_USB 167 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE 168 #endif /* CONFIG_CMD_USB */ 169 170 /* 171 * I2C related stuff 172 */ 173 #ifdef CONFIG_CMD_I2C 174 #define CONFIG_SYS_I2C 175 #define CONFIG_SYS_I2C_MVTWSI 176 #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE 177 #define CONFIG_SYS_I2C_SLAVE 0x0 178 #define CONFIG_SYS_I2C_SPEED 100000 179 #endif 180 181 /* 182 * Environment variables configurations 183 */ 184 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ 187 188 /* 189 * Size of malloc() pool 190 */ 191 #define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ 192 193 /* 194 * Other required minimal configurations 195 */ 196 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 197 #define CONFIG_NR_DRAM_BANKS 1 198 199 #define CONFIG_SYS_LOAD_ADDR 0x00800000 200 #define CONFIG_SYS_MEMTEST_START 0x00400000 201 #define CONFIG_SYS_MEMTEST_END 0x007fffff 202 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 203 204 /* Enable command line editing */ 205 #define CONFIG_CMDLINE_EDITING 206 207 /* provide extensive help */ 208 #define CONFIG_SYS_LONGHELP 209 210 /* additions for new relocation code, must be added to all boards */ 211 #define CONFIG_SYS_SDRAM_BASE 0 212 #define CONFIG_SYS_INIT_SP_ADDR \ 213 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 214 215 #endif /* _CONFIG_EDMINIV2_H */ 216