1 /* 2 * Configuation settings for the Renesas Solutions ECOVEC board 3 * 4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp. 5 * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __ECOVEC_H 12 #define __ECOVEC_H 13 14 /* 15 * Address Interface BusWidth 16 *----------------------------------------- 17 * 0x0000_0000 U-Boot 16bit 18 * 0x0004_0000 Linux romImage 16bit 19 * 0x0014_0000 MTD for Linux 16bit 20 * 0x0400_0000 Internal I/O 16/32bit 21 * 0x0800_0000 DRAM 32bit 22 * 0x1800_0000 MFI 16bit 23 */ 24 25 #define CONFIG_CPU_SH7724 1 26 #define CONFIG_ECOVEC 1 27 28 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000 29 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 30 31 #define CONFIG_CMD_SDRAM 32 #define CONFIG_CMD_ENV 33 34 #define CONFIG_BAUDRATE 115200 35 #define CONFIG_BOOTARGS "console=ttySC0,115200" 36 37 #define CONFIG_DISPLAY_BOARDINFO 38 #undef CONFIG_SHOW_BOOT_PROGRESS 39 40 /* I2C */ 41 #define CONFIG_SYS_I2C 42 #define CONFIG_SYS_I2C_SH 43 #define CONFIG_SYS_I2C_SLAVE 0x7F 44 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 45 #define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 46 #define CONFIG_SYS_I2C_SH_SPEED0 100000 47 #define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 48 #define CONFIG_SYS_I2C_SH_SPEED1 100000 49 #define CONFIG_SH_I2C_DATA_HIGH 4 50 #define CONFIG_SH_I2C_DATA_LOW 5 51 #define CONFIG_SH_I2C_CLOCK 41666666 52 53 /* Ether */ 54 #define CONFIG_SH_ETHER 1 55 #define CONFIG_SH_ETHER_USE_PORT (0) 56 #define CONFIG_SH_ETHER_PHY_ADDR (0x1f) 57 #define CONFIG_PHY_SMSC 1 58 #define CONFIG_PHYLIB 59 #define CONFIG_BITBANGMII 60 #define CONFIG_BITBANGMII_MULTI 61 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 62 63 /* USB / R8A66597 */ 64 #define CONFIG_USB_R8A66597_HCD 65 #define CONFIG_R8A66597_BASE_ADDR 0xA4D80000 66 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 67 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 68 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 69 #define CONFIG_SUPERH_ON_CHIP_R8A66597 70 71 /* undef to save memory */ 72 #define CONFIG_SYS_LONGHELP 73 /* Monitor Command Prompt */ 74 /* Buffer size for input from the Console */ 75 #define CONFIG_SYS_CBSIZE 256 76 /* Buffer size for Console output */ 77 #define CONFIG_SYS_PBSIZE 256 78 /* max args accepted for monitor commands */ 79 #define CONFIG_SYS_MAXARGS 16 80 /* Buffer size for Boot Arguments passed to kernel */ 81 #define CONFIG_SYS_BARGSIZE 512 82 /* List of legal baudrate settings for this board */ 83 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 84 85 /* SCIF */ 86 #define CONFIG_SCIF_CONSOLE 1 87 #define CONFIG_SCIF 1 88 #define CONFIG_CONS_SCIF0 1 89 90 /* Suppress display of console information at boot */ 91 92 /* SDRAM */ 93 #define CONFIG_SYS_SDRAM_BASE (0x88000000) 94 #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 95 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 96 97 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 98 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024) 99 /* Enable alternate, more extensive, memory test */ 100 #undef CONFIG_SYS_ALT_MEMTEST 101 /* Scratch address used by the alternate memory test */ 102 #undef CONFIG_SYS_MEMTEST_SCRATCH 103 104 /* Enable temporary baudrate change while serial download */ 105 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 106 107 /* FLASH */ 108 #define CONFIG_FLASH_CFI_DRIVER 1 109 #define CONFIG_SYS_FLASH_CFI 110 #undef CONFIG_SYS_FLASH_QUIET_TEST 111 #define CONFIG_SYS_FLASH_EMPTY_INFO 112 #define CONFIG_SYS_FLASH_BASE (0xA0000000) 113 #define CONFIG_SYS_MAX_FLASH_SECT 512 114 115 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 116 #define CONFIG_SYS_MAX_FLASH_BANKS 1 117 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 118 119 /* Timeout for Flash erase operations (in ms) */ 120 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 121 /* Timeout for Flash write operations (in ms) */ 122 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 123 /* Timeout for Flash set sector lock bit operations (in ms) */ 124 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 125 /* Timeout for Flash clear lock bit operations (in ms) */ 126 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 127 128 /* 129 * Use hardware flash sectors protection instead 130 * of U-Boot software protection 131 */ 132 #undef CONFIG_SYS_FLASH_PROTECTION 133 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 134 135 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 136 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 137 /* Monitor size */ 138 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 139 /* Size of DRAM reserved for malloc() use */ 140 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 141 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 142 143 /* ENV setting */ 144 #define CONFIG_ENV_IS_IN_FLASH 145 #define CONFIG_ENV_OVERWRITE 1 146 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 147 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 148 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 149 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 150 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 151 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 152 153 /* Board Clock */ 154 #define CONFIG_SYS_CLK_FREQ 41666666 155 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 156 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 157 #define CONFIG_SYS_TMU_CLK_DIV 4 158 159 #endif /* __ECOVEC_H */ 160