1 /* 2 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 3 * 4 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #ifndef _CONFIG_EB_CPU5282_H_ 26 #define _CONFIG_EB_CPU5282_H_ 27 28 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 29 30 /*----------------------------------------------------------------------* 31 * High Level Configuration Options (easy to change) * 32 *----------------------------------------------------------------------*/ 33 34 #define CONFIG_MCF52x2 /* define processor family */ 35 #define CONFIG_M5282 /* define processor type */ 36 37 #define CONFIG_MISC_INIT_R 38 39 #define CONFIG_MCFUART 40 #define CONFIG_SYS_UART_PORT (0) 41 #define CONFIG_BAUDRATE 115200 42 43 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 44 45 #define CONFIG_BOOTCOMMAND "printenv" 46 47 /*----------------------------------------------------------------------* 48 * Options * 49 *----------------------------------------------------------------------*/ 50 51 #define CONFIG_BOOT_RETRY_TIME -1 52 #define CONFIG_RESET_TO_RETRY 53 #define CONFIG_SPLASH_SCREEN 54 55 #define CONFIG_HW_WATCHDOG 56 57 #define CONFIG_STATUS_LED 58 #define CONFIG_BOARD_SPECIFIC_LED 59 #define STATUS_LED_ACTIVE 0 60 #define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */ 61 #define STATUS_LED_BOOT 0 62 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 63 #define STATUS_LED_STATE STATUS_LED_OFF 64 65 /*----------------------------------------------------------------------* 66 * Configuration for environment * 67 * Environment is in the second sector of the first 256k of flash * 68 *----------------------------------------------------------------------*/ 69 70 #define CONFIG_ENV_ADDR 0xFF040000 71 #define CONFIG_ENV_SECT_SIZE 0x00020000 72 #define CONFIG_ENV_IS_IN_FLASH 1 73 74 /* 75 * BOOTP options 76 */ 77 #define CONFIG_BOOTP_BOOTFILESIZE 78 #define CONFIG_BOOTP_BOOTPATH 79 #define CONFIG_BOOTP_GATEWAY 80 #define CONFIG_BOOTP_HOSTNAME 81 82 /* 83 * Command line configuration. 84 */ 85 #define CONFIG_CMDLINE_EDITING 86 #include <config_cmd_default.h> 87 88 #undef CONFIG_CMD_LOADB 89 #define CONFIG_CMD_DATE 90 #define CONFIG_CMD_DHCP 91 #define CONFIG_CMD_I2C 92 #define CONFIG_CMD_LED 93 #define CONFIG_CMD_MII 94 #define CONFIG_CMD_NET 95 96 #define CONFIG_MCFTMR 97 98 #define CONFIG_BOOTDELAY 5 99 #define CONFIG_SYS_PROMPT "\nEB+CPU5282> " 100 #define CONFIG_SYS_LONGHELP 1 101 102 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 104 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 105 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 106 107 #define CONFIG_SYS_LOAD_ADDR 0x20000 108 109 #define CONFIG_SYS_MEMTEST_START 0x100000 110 #define CONFIG_SYS_MEMTEST_END 0x400000 111 /*#define CONFIG_SYS_DRAM_TEST 1 */ 112 #undef CONFIG_SYS_DRAM_TEST 113 114 /*----------------------------------------------------------------------* 115 * Clock and PLL Configuration * 116 *----------------------------------------------------------------------*/ 117 #define CONFIG_SYS_HZ 1000 118 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 119 120 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 121 122 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 123 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 124 125 /*----------------------------------------------------------------------* 126 * Network * 127 *----------------------------------------------------------------------*/ 128 129 #define CONFIG_MCFFEC 130 #define CONFIG_MII 1 131 #define CONFIG_MII_INIT 1 132 #define CONFIG_SYS_DISCOVER_PHY 133 #define CONFIG_SYS_RX_ETH_BUFFER 8 134 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 135 136 #define CONFIG_SYS_FEC0_PINMUX 0 137 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 138 #define MCFFEC_TOUT_LOOP 50000 139 140 #define CONFIG_OVERWRITE_ETHADDR_ONCE 141 142 /*------------------------------------------------------------------------- 143 * Low Level Configuration Settings 144 * (address mappings, register initial values, etc.) 145 * You should know what you are doing if you make changes here. 146 *-----------------------------------------------------------------------*/ 147 148 #define CONFIG_SYS_MBAR 0x40000000 149 150 /*----------------------------------------------------------------------- 151 * Definitions for initial stack pointer and data area (in DPRAM) 152 *-----------------------------------------------------------------------*/ 153 154 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 155 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 156 #define CONFIG_SYS_GBL_DATA_OFFSET \ 157 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 158 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 159 160 /*----------------------------------------------------------------------- 161 * Start addresses for the final memory configuration 162 * (Set up by the startup code) 163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 164 */ 165 #define CONFIG_SYS_SDRAM_BASE0 0x00000000 166 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 167 168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 169 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 170 171 /* If M5282 port is fully implemented the monitor base will be behind 172 * the vector table. */ 173 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) 174 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 175 #else 176 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 177 #endif 178 179 #define CONFIG_SYS_MONITOR_LEN 0x20000 180 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 181 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 182 183 /* 184 * For booting Linux, the board info and command line data 185 * have to be in the first 8 MB of memory, since this is 186 * the maximum mapped by the Linux kernel during initialization ?? 187 */ 188 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 189 190 /*----------------------------------------------------------------------- 191 * FLASH organization 192 */ 193 #define CONFIG_FLASH_SHOW_PROGRESS 45 194 195 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 196 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 197 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 198 199 #define CONFIG_SYS_MAX_FLASH_SECT 128 200 #define CONFIG_SYS_MAX_FLASH_BANKS 1 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 202 #define CONFIG_SYS_FLASH_PROTECTION 203 204 #define CONFIG_SYS_FLASH_CFI 205 #define CONFIG_FLASH_CFI_DRIVER 206 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 207 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 208 209 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 210 211 /*----------------------------------------------------------------------- 212 * Cache Configuration 213 */ 214 #define CONFIG_SYS_CACHELINE_SIZE 16 215 216 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 217 CONFIG_SYS_INIT_RAM_SIZE - 8) 218 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 219 CONFIG_SYS_INIT_RAM_SIZE - 4) 220 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 221 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 222 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 223 CF_ACR_EN | CF_ACR_SM_ALL) 224 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 225 CF_CACR_CEIB | CF_CACR_DBWE | \ 226 CF_CACR_EUSP) 227 228 /*----------------------------------------------------------------------- 229 * Memory bank definitions 230 */ 231 232 #define CONFIG_SYS_CS0_BASE 0xFF000000 233 #define CONFIG_SYS_CS0_CTRL 0x00001980 234 #define CONFIG_SYS_CS0_MASK 0x00FF0001 235 236 #define CONFIG_SYS_CS2_BASE 0xE0000000 237 #define CONFIG_SYS_CS2_CTRL 0x00001980 238 #define CONFIG_SYS_CS2_MASK 0x000F0001 239 240 #define CONFIG_SYS_CS3_BASE 0xE0100000 241 #define CONFIG_SYS_CS3_CTRL 0x00001980 242 #define CONFIG_SYS_CS3_MASK 0x000F0001 243 244 /*----------------------------------------------------------------------- 245 * Port configuration 246 */ 247 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 248 #define CONFIG_SYS_PADDR 0x0000000 249 #define CONFIG_SYS_PADAT 0x0000000 250 251 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 252 #define CONFIG_SYS_PBDDR 0x0000000 253 #define CONFIG_SYS_PBDAT 0x0000000 254 255 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 256 #define CONFIG_SYS_PCDDR 0x0000000 257 #define CONFIG_SYS_PCDAT 0x0000000 258 259 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 260 #define CONFIG_SYS_PCDDR 0x0000000 261 #define CONFIG_SYS_PCDAT 0x0000000 262 263 #define CONFIG_SYS_PASPAR 0x0F0F 264 #define CONFIG_SYS_PEHLPAR 0xC0 265 #define CONFIG_SYS_PUAPAR 0x0F 266 #define CONFIG_SYS_DDRUA 0x05 267 #define CONFIG_SYS_PJPAR 0xFF 268 269 /*----------------------------------------------------------------------- 270 * I2C 271 */ 272 273 #define CONFIG_HARD_I2C 274 #define CONFIG_FSL_I2C 275 276 #define CONFIG_SYS_I2C_OFFSET 0x00000300 277 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 278 279 #define CONFIG_SYS_I2C_SPEED 100000 280 #define CONFIG_SYS_I2C_SLAVE 0 281 282 #ifdef CONFIG_CMD_DATE 283 #define CONFIG_RTC_DS1338 284 #define CONFIG_I2C_RTC_ADDR 0x68 285 #endif 286 287 /*----------------------------------------------------------------------- 288 * VIDEO configuration 289 */ 290 291 #define CONFIG_VIDEO 292 293 #ifdef CONFIG_VIDEO 294 #define CONFIG_VIDEO_VCXK 1 295 296 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 297 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 298 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 299 300 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 301 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 302 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 303 304 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 305 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 306 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 307 308 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 309 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 310 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 311 312 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 313 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 314 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 315 316 #endif /* CONFIG_VIDEO */ 317 #endif /* _CONFIG_M5282EVB_H */ 318 /*---------------------------------------------------------------------*/ 319