1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 4 * 5 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 6 */ 7 8 #ifndef _CONFIG_EB_CPU5282_H_ 9 #define _CONFIG_EB_CPU5282_H_ 10 11 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 12 13 /*----------------------------------------------------------------------* 14 * High Level Configuration Options (easy to change) * 15 *----------------------------------------------------------------------*/ 16 17 #define CONFIG_MISC_INIT_R 18 19 #define CONFIG_MCFUART 20 #define CONFIG_SYS_UART_PORT (0) 21 22 #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 23 24 #define CONFIG_BOOTCOMMAND "printenv" 25 26 /*----------------------------------------------------------------------* 27 * Options * 28 *----------------------------------------------------------------------*/ 29 30 #define CONFIG_BOOT_RETRY_TIME -1 31 #define CONFIG_RESET_TO_RETRY 32 #define CONFIG_SPLASH_SCREEN 33 34 #define CONFIG_HW_WATCHDOG 35 36 #define STATUS_LED_ACTIVE 0 37 38 /*----------------------------------------------------------------------* 39 * Configuration for environment * 40 * Environment is in the second sector of the first 256k of flash * 41 *----------------------------------------------------------------------*/ 42 43 #define CONFIG_ENV_ADDR 0xFF040000 44 #define CONFIG_ENV_SECT_SIZE 0x00020000 45 46 /* 47 * BOOTP options 48 */ 49 #define CONFIG_BOOTP_BOOTFILESIZE 50 51 /* 52 * Command line configuration. 53 */ 54 55 #define CONFIG_MCFTMR 56 57 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 58 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 59 60 #define CONFIG_SYS_LOAD_ADDR 0x20000 61 62 #define CONFIG_SYS_MEMTEST_START 0x100000 63 #define CONFIG_SYS_MEMTEST_END 0x400000 64 /*#define CONFIG_SYS_DRAM_TEST 1 */ 65 #undef CONFIG_SYS_DRAM_TEST 66 67 /*----------------------------------------------------------------------* 68 * Clock and PLL Configuration * 69 *----------------------------------------------------------------------*/ 70 #define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 71 72 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 73 74 #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 75 #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 76 77 /*----------------------------------------------------------------------* 78 * Network * 79 *----------------------------------------------------------------------*/ 80 81 #define CONFIG_MCFFEC 82 #define CONFIG_MII 1 83 #define CONFIG_MII_INIT 1 84 #define CONFIG_SYS_DISCOVER_PHY 85 #define CONFIG_SYS_RX_ETH_BUFFER 8 86 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 87 88 #define CONFIG_SYS_FEC0_PINMUX 0 89 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 90 #define MCFFEC_TOUT_LOOP 50000 91 92 #define CONFIG_OVERWRITE_ETHADDR_ONCE 93 94 /*------------------------------------------------------------------------- 95 * Low Level Configuration Settings 96 * (address mappings, register initial values, etc.) 97 * You should know what you are doing if you make changes here. 98 *-----------------------------------------------------------------------*/ 99 100 #define CONFIG_SYS_MBAR 0x40000000 101 102 /*----------------------------------------------------------------------- 103 * Definitions for initial stack pointer and data area (in DPRAM) 104 *-----------------------------------------------------------------------*/ 105 106 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 107 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 108 #define CONFIG_SYS_GBL_DATA_OFFSET \ 109 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 112 /*----------------------------------------------------------------------- 113 * Start addresses for the final memory configuration 114 * (Set up by the startup code) 115 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 116 */ 117 #define CONFIG_SYS_SDRAM_BASE0 0x00000000 118 #define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 119 120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 121 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 122 123 #define CONFIG_SYS_MONITOR_LEN 0x20000 124 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 125 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 126 127 /* 128 * For booting Linux, the board info and command line data 129 * have to be in the first 8 MB of memory, since this is 130 * the maximum mapped by the Linux kernel during initialization ?? 131 */ 132 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 133 134 /*----------------------------------------------------------------------- 135 * FLASH organization 136 */ 137 #define CONFIG_FLASH_SHOW_PROGRESS 45 138 139 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 140 #define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 141 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 142 143 #define CONFIG_SYS_MAX_FLASH_SECT 128 144 #define CONFIG_SYS_MAX_FLASH_BANKS 1 145 #define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 146 #define CONFIG_SYS_FLASH_PROTECTION 147 148 #define CONFIG_SYS_FLASH_CFI 149 #define CONFIG_FLASH_CFI_DRIVER 150 #define CONFIG_SYS_FLASH_SIZE 16*1024*1024 151 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 152 153 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 154 155 /*----------------------------------------------------------------------- 156 * Cache Configuration 157 */ 158 #define CONFIG_SYS_CACHELINE_SIZE 16 159 160 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 161 CONFIG_SYS_INIT_RAM_SIZE - 8) 162 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 163 CONFIG_SYS_INIT_RAM_SIZE - 4) 164 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 165 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 166 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 167 CF_ACR_EN | CF_ACR_SM_ALL) 168 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 169 CF_CACR_CEIB | CF_CACR_DBWE | \ 170 CF_CACR_EUSP) 171 172 /*----------------------------------------------------------------------- 173 * Memory bank definitions 174 */ 175 176 #define CONFIG_SYS_CS0_BASE 0xFF000000 177 #define CONFIG_SYS_CS0_CTRL 0x00001980 178 #define CONFIG_SYS_CS0_MASK 0x00FF0001 179 180 #define CONFIG_SYS_CS2_BASE 0xE0000000 181 #define CONFIG_SYS_CS2_CTRL 0x00001980 182 #define CONFIG_SYS_CS2_MASK 0x000F0001 183 184 #define CONFIG_SYS_CS3_BASE 0xE0100000 185 #define CONFIG_SYS_CS3_CTRL 0x00001980 186 #define CONFIG_SYS_CS3_MASK 0x000F0001 187 188 /*----------------------------------------------------------------------- 189 * Port configuration 190 */ 191 #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 192 #define CONFIG_SYS_PADDR 0x0000000 193 #define CONFIG_SYS_PADAT 0x0000000 194 195 #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 196 #define CONFIG_SYS_PBDDR 0x0000000 197 #define CONFIG_SYS_PBDAT 0x0000000 198 199 #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 200 #define CONFIG_SYS_PCDDR 0x0000000 201 #define CONFIG_SYS_PCDAT 0x0000000 202 203 #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 204 #define CONFIG_SYS_PCDDR 0x0000000 205 #define CONFIG_SYS_PCDAT 0x0000000 206 207 #define CONFIG_SYS_PASPAR 0x0F0F 208 #define CONFIG_SYS_PEHLPAR 0xC0 209 #define CONFIG_SYS_PUAPAR 0x0F 210 #define CONFIG_SYS_DDRUA 0x05 211 #define CONFIG_SYS_PJPAR 0xFF 212 213 /*----------------------------------------------------------------------- 214 * I2C 215 */ 216 217 #define CONFIG_SYS_I2C 218 #define CONFIG_SYS_I2C_FSL 219 220 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 221 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 222 223 #define CONFIG_SYS_FSL_I2C_SPEED 100000 224 #define CONFIG_SYS_FSL_I2C_SLAVE 0 225 226 #ifdef CONFIG_CMD_DATE 227 #define CONFIG_RTC_DS1338 228 #define CONFIG_I2C_RTC_ADDR 0x68 229 #endif 230 231 /*----------------------------------------------------------------------- 232 * VIDEO configuration 233 */ 234 235 #ifdef CONFIG_VIDEO 236 #define CONFIG_VIDEO_VCXK 1 237 238 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 239 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 240 #define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 241 242 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 243 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 244 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 245 246 #define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 247 #define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 248 #define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 249 250 #define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 251 #define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 252 #define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 253 254 #define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 255 #define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 256 #define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 257 258 #endif /* CONFIG_VIDEO */ 259 #endif /* _CONFIG_M5282EVB_H */ 260 /*---------------------------------------------------------------------*/ 261